Jeffery C. C. Lo

Process development and prototyping for the assembly of LED arrays on flexible printed circuit tape for general solid state lighting

The objective of the present study is to develop a robust high-throughput assembly process of light emitting diode arrays for wide area general lighting. Topics to be covered in this paper include the conceptual design, the flexible printed circuit substrate, flip chip assembly, yellow phosphor coating, and encapsulation. All these are integrated into one reel-to-reel assembly process. A prototype with the proposed process has been developed. A sample strip of packaged LED array has been produced as well to validate the developed assembly process.

Material characterization of corner and edgebond epoxy adhesives for the improvement of board-level solder joint reliability

In this paper, the material characteristics of six epoxies used for corner/edge-bonding are analyzed and compared to board-level mechanical reliability test. An innovative material characterization approach, button shear testing, provided an expedient method of determining adhesive strength between the epoxies and each relevant surface material. The board-level test included mechanical shock test. A number of SMT test devices are evaluated, including 1849 CBGA packages, and 190 ball count mezzanine connectors. The failure modes and fracture strengths of the material characterization tests and board-level tests are cross-referenced for comparison, and assessed for correlation. The results from the present study not only contribute to the characterization and selection methods of corner/edge-bonding epoxies, but also improve understanding of the corresponding relationship between material characterization testing and the more complex and costly board-level reliability tests.

Reliability study of surface mount printed circuit board assemblies with lead‐free solder joints

Purpose – The purpose of this paper is to evaluate the lead‐free solder joint reliability of a variety of surface mount components assembled onto printed circuit boards (PCBs) under a number of different tests.Design/methodology/approach – Lead‐free solder with a composition of Sn96.5‐Ag3.0‐Cu0.5 was used in a surface mount reflow process. Different types of surface mount dummy components with a daisy chain, such as CBGAs, BGAs, PLCCs, CSPs, and QFNs, were assembled onto PCBs. Both the mechanical and thermo‐mechanical reliability of the solder joints were evaluated by several tests. The experiments included package shear, package pull, three‐point bending and accelerated thermal cycling testing for 2,000 cycles. The packages were examined by X‐ray and C‐SAM before the reliability tests were carried out. The maximum load and the corresponding load‐displacement curve were recorded in the mechanical test.Findings – The results from the mechanical tests show the major failure mode is on the copper pad. Weibul...

Lens Forming by Stack Dispensing for LED Wafer Level Packaging

In this paper a moldless stack dispensing method to form an LED lens at the wafer level is presented. This method uses a dispensing process to form a lens with high H/L ratio, where H and L stand for the height and the base length of the lens. Silicon wafer is used as the substrate. V-groove trenches are made on the surface of the wafer to define the size of the substrates. In the dispensing process a droplet of encapsulant is dispensed on the substrate to form a base heap. After the base heap is cured, a second droplet of encapsulant is dispensed on top of the base heap and cured. The stacked encapsulant forms a lens with high H/L ratio. Dispensing on substrates sized from 3mm × 3mm to 5mm × 5mm is investigated. For each size of substrate, experiments are performed to obtain the maximum volume of the encapsulant without overflowing (the critical volume) for both the base heap and the stacked layer. The results show that despite size differences, substrates of different sizes have a similar critical volume for both the base heap and the stacked layer. The ratio of critical volume of base heap to stacked layer remains at around 1:1. Consequently, the highest H/L values of substrates with different sizes stay at around 0.33. Both critical k and H/L show no obvious correlation to the size of substrate.

Characterization of orthotropic CTE of BT substrate for PBGA warpage evaluation

Material characterization is a crucial part of BGA thermal warpage evaluation. In principle, the warpage behavior of BGA under temperature change is affected by the elastic modulus and the coefficient of thermal expansion (CTE) of the packaging materials. Therefore, the accuracy of material properties is critical for predicting the warpage trend and quantity. However, due to the rather thin BT substrate, it is difficult to measure the accurate orthotropic CTE in the planar direction using the conventional TMA method. This study proposes a new method to estimate the CTE of the BT substrate in PBGA devices. The required sample is cut into strips, which are bi-material beams containing the BT laminate and EMC of a PBGA. The concept of Stoneys formula is employed to establish the relations of the CTE, the curvature and other parameters of the sample. Through this method, the CTE of the BT substrate is measured using a dynamic mechanical analyzer (DMA) and calculated as a function of temperature, giving a more accurate description than the conventional temperature dependent CTE. A simulation study and the corresponding mechanism analysis are also given in this paper. With the estimated BT substrate CTE and other material properties (including elastic moduli and CTE of EMC), the warpage simulation is performed in the FEA model of the bi-material beam as a sub-model of the PBGA device to estimate the warpage behavior. From the comparison of the simulation and experiment results, the measured material properties and calculated BT CTE could lead to a reasonable prediction of warpage in both the qualitative and quantitative senses. The proposed methodology may be used for academic research and industrial applications.

Correlation of board and joint level test methods with strain dominant failure criteria for improving the resistance to pad cratering

Due to the advantages of joint level tests, such as low cost and flexibility, it is always desirable to predict the board level pad cratering strength by a joint level test. In order to achieve this objective, the correlation between the joint level and the board level tests must be fully understood. Nevertheless, a precise correlation between the two types of tests for pad cratering evaluation is yet to be defined. This study investigates the correlation methodology of critical failure factors between joint and board level tests on pad cratering failure mode. An intermediate critical failure factor is taken from joint level testing as a failure criterion for failure prediction in board level testing. From the results of the experimental study and finite element analysis (FEA), the critical failure factor correlation is established between the board level and the joint level test. Subsequently the obtained failure criterion is also verified by a board level experimental study. In consequence, this indirect correlation method has the capability to predict the board level pad cratering failure with various geometric parameters.

Parameter Correlation and Computational Modeling for the Flow of Encapsulant in Through-Silicon-Via Underfill Dispensing

This paper introduces a through-silicon-via (TSV) dispensing approach to accomplish the underfill process without a conventional reservoir. The vias function as entrances for dispensing or paths for fluid flow. Typically, the inflows of dispensing can be free droplets or a constant flow rate. The underfill flow in the gap includes two flowing stages: 1) the initial bidirectional flow and 2) the subsequent flow along chip edges. To find the factors affecting the filling time in TSV underfill, an analytical model is first built for the initial bidirectional underfill flow. The bidirectional flow is approximately modeled as a laminar and quasi-steady creeping flow between two parallel plates. The filling time in the initial stage is closely related to the flow radius, the inlet boundary, the material properties, the gap geometry, and the bump pattern. Afterward, the subsequent flow along the chip edges is investigated using a computational multiphase model. The governing equations of the computational model consist of mass conversation, momentum conversation, and element volume conservation. The computational results show that the chip length-width ratio also has a significant impact on the filling time if the inflow is free droplets.

Lens forming by stack dispensing for LED wafer level packaging

In this paper, a moldless stack dispensing method to form an light-emitting diode (LED) lens at the wafer level is presented. This method uses a dispensing process to form a lens with high H/L ratio, where H and L stand for the height and the base length of the lens. Silicon wafer is used as the substrate. V-groove trenches are made on the surface of the wafer to define the size of the substrates. In the dispensing process, a droplet of encapsulant is dispensed on the substrate to form a base heap. After the base heap is cured, a second droplet of encapsulant is dispensed on top of the base heap and cured. The stacked encapsulant forms a lens with high H/L ratio. Dispensing on substrates sized from 3 mm × 3 mm to 5 mm × 5 mm is investigated. For each size of substrate, experiments are performed to obtain the maximum volume of the encapsulant without overflowing (the critical volume) for both the base heap and the stacked layer. The results show that despite size differences, substrates of different sizes have a similar critical volume for both the base heap and the stacked layer. The ratio of critical volume of base heap to stacked layer remains at around 1:1. Consequently, the highest H/L values of substrates with different sizes stay at around 0.33. Both critical k and H/L show no obvious correlation to the size of substrate. The method is implemented on a functional LED package. Investigations on the geometry of the lens and optical characteristics of the encapsulated LED packages are shown. The results show that the stacked encapsulation modifies the light distribution and improves the radiant power of an LED package.

Development of a real-time monitoring system with uni-photodetector for LED long term reliability tests

In this paper, a fully automated, low-cost, real-time illuminance measurement system for LED long term reliability tests is proposed. The system has only one photodetector to measure the illuminance of all samples inside the test chamber during the reliability test. With a proprietary algorithm, a single photodetector can measure the illuminance of all samples in the chamber by sequential scanning. This system monitors and records the illuminance of each individual sample inside the test chamber. This provides continuous and reliable data for analysis and prediction of LED lifespan. It does not require suspending the reliability test for sample inspection and can automatically analyze the time-to-failure of samples. The proposed system can significantly reduce the time required for data acquisition and measurement errors. This paper also compares the results obtained from the proposed system and the conventional periodic inspection to highlight the merits of the new system.

LED wafer level packaging with a remote phosphor cap

Phosphor converted LEDs (pc-LEDs), which employ yellow phosphor deposited on blue LEDs to generate white light illumination have been widely used in solid-state lighting (SSL). Currently most LEDs are packaged on an individual component basis. Such a conventional packaging process typically may have a relatively low throughput and poor uniformity. In this paper, a new structure for 3D wafer level LED packaging is introduced. The package consists of three parts: a silicon submount wafer with pre-mounted LEDs, a silicon cap wafer, and a layer of phosphor film. Each part was independently fabricated and subsequently assembled at the wafer level. The optical performance of singulated prototypes was characterized using an integrating sphere. Comparison and discussion of samples with various phosphor-silicone mixing ratios are given in detail.