Saad Bin Nasir

5.6 A 0.13μm fully digital low-dropout regulator with adaptive control and reduced dynamic stability for ultra-wide dynamic range

This paper presents a discrete-time, fully digital, scan-programmable LDO macro in 0.13μm technology featuring greater than 90% current efficiency across a 50× current range, and 8× improvement in transient response time in response to large load steps. The baseline design features a 128b barrel shifter that digitally controls 128 identical power PMOS devices to provide load and line regulation at the node VREG, for a scan-programmable fine-grained synthetic load. A clocked comparator, which eliminates the need for any bias current, controls the direction of shift, D. The programmable mux-select signals, MUX1 and MUX2, provide controllable closed loop gains, KBARREL, of 1 to 3×. Since at any clock edge only 1, 2 or 3 shifts can occur (depending on the gain setting), fine-grained clock gating is enabled by dividing the 128b shifter into four sections and only enabling the clock to the section(s) where the shift occurs.

Modeling and analysis of digital linear dropout regulators with adaptive control for high efficiency under wide dynamic range digital loads

Discrete time digital linear regulators, including low dropout regulators (LDOs) have become competitive in muti-Vcc digital systems for fine-grained spatio-temporal voltage regulation and distribution. However, wide dynamic current range of the digital load circuits poses serious problems in maintaining stability and high efficiency at all corners. In this paper we present a control model for discrete time LDOs and demonstrate how online adaptive control can be employed for consistent performance and high efficiency across the load current range.

On limit cycle oscillations in discrete-time digital linear regulators

Increasing level of transistor integration with multiple voltage domains and power states, ever decreasing decoupling capacitance, fast load transients and the need for fine-grained spatio-temporal power management provide impetus for embedding distributed point of load (PoL) linear regulators deep within digital functional blocks of microprocessors and Systems-on-Chip (SoCs). This demands modularity in design as well as process and voltage scalability of such linear regulators. Digital linear regulators have emerged as an attractive counterpart to the traditional analog solutions. This paper presents the circuit implementation and a steady state response model of a discrete-time digital regulator with simulations and hardware measurements with an emphasis on the steady state oscillations. We develop parametric models to demonstrate design trade-offs for a stable steady state response.

All-Digital Low-Dropout Regulator With Adaptive Control and Reduced Dynamic Stability for Digital Load Circuits

Digitally implementable LDOs embedded within digital functional units augment their analog counterparts for ultrafine-grained power management in digital ICs. Digital load circuits represent load currents with large and in frequent current transients and require a wide voltage range of operation, preferably down to the threshold voltage (VTH) of the transistor. This paper presents a discrete-time, fully digital, scan-programmable LDO macro in a low-power 0.13-μm technology operating down to 1.07×, the transistor VTH, and featuring greater than 90% current efficiency across a 50× current range through fine-grained clock gating and adaptive control. An 8× improvement in transient response time to large load steps is achieved through switched mode control. Both transient and steady-state operation models and measurements of the LDO are presented.

Integrated power management in IoT devices under wide dynamic ranges of operation

By the year 2020 it is expected that corresponding to every human being there would be seven connected devices. These connected devices will usher in the Internet of Things (IoTs) and would percolate every aspect of human life, changing the human experience at a fundamental level. In order to power these devices novel strategies would have to be developed as these devices will not only have a dynamic load, due to multiple features, but also dynamic sources if opportunistic energy harvesting is used to supplement the rechargeable battery. For the power delivery network, figures of merit would be to comprehend both the ability to supply the worst case design as well as to maintain high efficiency across a wide dynamic range. To maintain high efficiency for a large range we will need adaptive components on the load side as well as at the energy source. In this work we will discuss the general IoT power delivery network (PDN), current research and the state of the art PDN components, novel designs and control for interface circuits and energy harvesters.

Modeling and analysis of system stability in a distributed power delivery network with embedded digital linear regulators

On-chip power delivery networks (PDNs) for todays microprocessors and systems-on-chip (SoCs), which are characterized by dynamic supply voltage, many embedded integrated VRs (IVRs), lower decoupling-capacitor, high current ranges, multiple power modes and fast transient loads are designed to minimize AC load transients and supply noise. The close interaction of the VRs with the power grids create multiple feedback paths in the overall network, compromising the resultant phase margin and can even lead to system instabilities. The introduction of digital linear regulators operating in the low dropout (LDO) mode, with low power supply rejection, further exacerbates the problem. This paper provides a comprehensive methodology, based on Masons Gain Formula applied to hybrid control, for modeling and analyzing distributed linear regulators and their interaction with the PDN.

A 130nm hybrid low dropout regulator based on switched mode control for digital load circuits

A hybrid (digital and analog) low dropout regulator (LDO) utilizing switched mode control is designed in 130 nm CMOS for fine grain power management, fast droop recovery and robust small signal regulation of multi-VCC digital loads. The design provides an optimal trade-off of performance and accuracy by switching between a digital and an analog control loop. The hybrid topology achieves robust small signal regulation and fast recovery from large signal transients or power state transitions. Measurements from a 130nm test-chip show Near-Threshold Voltage (NTV) operation, fast transient response of 18 ns for a load step of 10.3mA and a peak current efficiency of 98.64%.

High efficiency power side-channel attack immunity using noise injection in attenuated signature domain

With the advancement of technology in the last few decades, leading to the widespread availability of miniaturized sensors and internet-connected things (IoT), security of electronic devices has become a top priority. Side-channel attack (SCA) is one of the prominent methods to break the security of an encryption system by exploiting the information leaked from the physical devices. Correlational power attack (CPA) is an efficient power side-channel attack technique, which analyses the correlation between the estimated and measured supply current traces to extract the secret key. The existing countermeasures to the power attacks are mainly based on reducing the SNR of the leaked data, or introducing large overhead using techniques like power balancing. This paper presents an attenuated signature AES (AS-AES), which resists SCA with minimal noise current overhead. AS-AES uses a shunt low-drop-out (LDO) regulator to suppress the AES current signature by 400x in the supply current traces. The shunt LDO has been fabricated and validated in 130 nm CMOS technology. System-level implementation of the AS-AES along with noise injection, shows that the system remains secure even after 50K encryptions, with 10x reduction in power overhead compared to that of noise addition alone.

Self-Optimizing IoT Wireless Video Sensor Node With In-Situ Data Analytics and Context-Driven Energy-Aware Real-Time Adaptation

It is well understood that data-acquisition by distributed sensors and subsequent transmission of all the acquired data to the cloud will produce a “data deluge” in next-generation wireless networks leading to immense network congestion, and data back-logs on the server which will prevent real-time processing and control. This motivates in situ data analytics in energy-constrained wireless sensor nodes that can perform context-aware acquisition and processing of data; and transmit data only when required. This paper presents a camera-based wireless sensor node with a self-optimizing end-to-end computation and communication design, targeted for surveillance applications. We demonstrate support for multiple feature-extraction and classification algorithms, tunable processing depth and power amplifier gain. Depending on the amount of information content, accuracy targets and condition of the wireless channel, the system choses the minimum-energy operating-point by dynamically optimizing the amount of processing done on the sensor itself. We demonstrate a complete system with ADI ADSP-BF707 image processor, OV7670 camera sensor, and USRP B200 software defined radio; and achieve

In-sensor analytics and energy-aware self-optimization in a wireless sensor node

4.3\times