Shreyas Sen

A 4–32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS

This paper details the design of an 8-lane bidirectional link for both within-the-box and external communications in 22 nm CMOS technology. A low profile connector with a high density cable assembly ensure a data rate of up to 32 Gb/s per lane while maintaining channel loss below 25 dB. Channel equalization is performed by a combination of a 3-tap feed-forward equalizer (FFE), single-stage continuous-time linear equalizer (CTLE) and a 6-tap decision-feedback equalizer (DFE). Collaborative timing recovery is used to enable lane characterization without degrading jitter performance. Phase error decimation, with a conditional phase detection scheme, is used to reduce the DFE complexity by 50%. Power consumption over a wide range of data rates from 4 to 32 Gb/s is reduced by using regulated CMOS clocking with lane bundling, low swing transmitter with a source-series terminated (SST) driver and a highly reconfigurable receiver with an active inductor CTLE. At a lane data rate of 32 Gb/s, over a 0.5 m cable with 16 dB of loss, a transceiver lane consumes 205 mW from a 1.07 V supply. The power scales down to 26 mW from a 0.72 V supply at 8 Gb/s, when transmitting over a channel with 8 dB loss. The active silicon area per lane is 0.079 mm2.

Concurrent Device/Specification Cause–Effect Monitoring for Yield Diagnosis Using Alternate Diagnostic Signatures

In this paper, an efficient methodology for die level test-and-diagnosis for Analog/RF circuits is developed. The key contribution of this work lies in the ability to both determine the DUT specifications as well as the underlying Spice-level model parameters from the same DUT test response on a per chip basis, thereby providing quicker and higher diagnostic resolution. The test and diagnosis procedures are enabled by a new computationally efficient test stimulus generation algorithm that simultaneously targets test sensitivity and parameter model diagnosability. This allows cause-effect analysis to be performed that relates perturbations in the spice-level model parameters to the DUT performance metrics (specifications). Further, cause-effect diagnosis is achieved at a test cost comparable to prior testing schemes that target only pass/ fail classification of tested devices.

Real-time use-aware adaptive MIMO RF receiver systems for energy efficiency under BER constraints

Modern MIMO RF transceiver systems are designed to operate reliably under diverse channel conditions leading to incorporation of significant performance margins in RF transceiver systems. In general, across dynamically varying channel conditions, the fidelity of the RF front end devices can be traded-off against power consumption without compromising system-level BER limits. In this work such a real-time performance vs. power consumption modulation of RF front-end devices in MIMO systems is demonstrated. Through a multi-dimensional optimization technique, power-optimal configuration of the frontend for varying channel conditions are created. Additionally multiple low-power operating modes for the MIMO system are proposed depending on the performance metric (data rate or energy-per-bit) that need to be optimized for different applications.

Low Cost EVM Testing of Wireless RF SoC Front-Ends Using Multitones

Error-vector-magnitude (EVM) is a system level specification that determines the overall modulation quality and exhibits strong correlation to the inherent nonidealities of a radio frequency (RF) system. In production testing, EVM tests incur significant cost due to the large number of symbols required to ensure test quality. In our approach, EVM is decomposed into its deterministic (due to static impairments: IQ mismatch, gain, AM-AM and AM-PM) and random (due to dynamic impairments: VCO phase noise, thermal noise) components. The static impairments are computed from the device under test (DUT) response to an optimized multitone test input. The dynamic impairments are computed using signal processing algorithms from the DUT test response to the same test input. The EVM of the RF system is then derived from the computed static and dynamic impairments, respectively. Experimental results show that significant reduction in test time is possible without compromising EVM test quality.

26.2 A 205mW 32Gb/s 3-Tap FFE/6-tap DFE bidirectional serial link in 22nm CMOS

Peripheral I/O data-rates for PCs and mobile computing platforms continue to scale to meet high-bandwidth applications including high-resolution displays and large-capacity external storage. The bandwidth requirements will soon exceed the data-rates of current standards such as PCI Express and USB. A low-power low-cost serial link is needed for the next-generation peripheral interface that can scale to 32Gb/s per lane. Recent publications have demonstrated 28 to 32Gb/s rates [1-2]. However, the circuit power and channel characteristics are not suitable for mainstream PC and mobile markets. A low-profile connector and cable assembly prototype is developed for these markets, where the link architecture and design are optimized for the channel characteristics. This paper describes a data-rate-scalable 32Gb/s serial link that features a bidirectional transceiver, source-series terminated (SST) 3-tap FFE, a continuous-time linear equalizer (CTLE) with an active inductor, a 6-tap DFE, and clock calibration and adaptation circuitry.

26.4 A 25.6Gb/s differential and DDR4/GDDR5 dual-mode transmitter with digital clock calibration in 22nm CMOS

A wide range of memory configurations exist in todays high-speed digital systems to meet platform-specific bandwidth, power, capacity, and cost constraints. In the near term, DDR4 and GDDR5 are expected to meet the needs of server, client, graphics and mobile platforms [1]. Differential signaling with high-speed serial I/O enhancements will potentially continue I/O performance scaling for post-DDR4 and future buffered memory solutions. A unified memory interface that can meet the signaling requirements of all these memory standards offers several benefits: reduced cost and design time, greater platform design flexibility, and a smoother transition from DDR4/GDDR5 to a high-speed differential memory interface [2]. This paper presents a dual-mode TX that supports single-ended (SE) 1.2V-DDR4/1.5V-GDDR5 (hereafter referred to as DDR-mode) as well as high-speed differential signaling (hereafter referred to as HSD-mode), which is implemented using only thin-gate-oxide devices in 22nm CMOS. Other key design features include: (a) a DDR4/GDDR5 driver implemented using only active devices (no linearizing resistors), (b) enhanced voltage-mode driver supply regulation, (c) reconfigurable logic to support pre-emphasis in both TX modes, and (d) low-overhead digital clock-calibration techniques based on asynchronous digital sampling (ADS) to improve calibration coverage and accuracy.

Measurement of envelope/phase path delay skew and envelope path bandwidth in polar transmitters

Polar transmitters are desirable for portable devices due to higher power efficiency they provide compared to traditional Cartesian transmitters. However, the difference in architecture results in differences in potential circuit impairments/fault models, leading to different test/measurement/calibration requirements. The delay skew between the envelope and phase signals and the finite envelope bandwidth can create inter modulation distortion that leads to the violation of the spectral mask and error vector magnitude (EVM) requirements. Therefore, measurement and compensation/calibration of these parameters are important to ensure proper operation for the polar transmitter. In this paper, we propose a technique to measure the delay skew and the finite envelope bandwidth based on the measurement of the 3rd order inter modulation distortion (IMD3) at the output of the transmitter. First, a two-tone input at a sufficiently low frequency is applied to the transmitter baseband input to calculate the delay. Then, we apply another two-tone input at a relatively higher frequency to determine the envelope bandwidth. Simulation and hardware measurement results show that the proposed technique can characterize the targeted impairments in the polar transmitter accurately within 10ms which is negligible compared to signal source switching and settling times.

23.2 A 32Gb/s bidirectional 4-channel 4pJ/b capacitively coupled link in 14nm CMOS for proximity communication

Board-to-board near mm-range proximity communication offers connector-less, sealed energy-efficient high-speed interfaces for computing devices. This work presents a 4-channel 4 pJ/b capacitively coupled interface supporting an aggregate data-rate of 32 Gb/s up to a 0.8 mm air gap. By employing a self-crosstalk cancelling coupler and self-resonance mitigating IC design, the prototype enables board-to-board high-density bidirectional signaling capability.

Self Learning Analog/Mixed-Signal/RF Systems: Dynamic Adaptation to Workload and Environmental Uncertainties

Real-time systems for wireless communication, digital signal processing and control experience a wide gamut of operating conditions (signal/channel noise, workload demand, perturbed process conditions). As device bandwidths expand, it becomes increasingly expensive, from a power consumption and reliability perspective, to operate such real-time systems for worst-case (static) performance requirements. In contrast, it is attractive to design algorithms, architectures and circuits that are power-performance tunable and can adapt dynamically, via self-learning techniques, to the requirements of system-level applications for extended battery usage and device lifetime. Such future systems will feed application level demands to the underlying algorithm-architecture-circuit design fabric through built-in sense-and-control infrastructure (hardware, software). The sense functions assess instantaneous application level demands (e.g. throughput, signal integrity) as well as the performances of the individual hardware components as determined by manufacturing process conditions. The control functions actuate algorithm-through-circuit level tuning knobs that continuously trade off performance vs. power of the individual software and hardware modules in such a way as to deliver the end-to-end desired application level Quality of Service (QoS), while minimizing energy/power consumption. Application to wireless communications systems, digital signal processing and control algorithms is discussed.

A 32 Gb/s Bidirectional 4-channel 4 pJ/b Capacitively Coupled Link in 14 nm CMOS for Proximity Communication

Board-to-board near mm-range proximity communication offers connector-less, sealed energy-efficient high-speed interfaces for computing devices. This work presents a 4-channel 4 pJ/b capacitively coupled interface supporting an aggregate data-rate of 32 Gb/s up to a 0.8 mm air gap. By employing a self-crosstalk cancelling coupler and self-resonance mitigating IC design, the prototype enables board-to-board high-density bidirectional signaling capability.