Sachin Kumar Rajput

Two-stage high gain low power OpAmp with current buffer compensation

This paper presents the classic two stage CMOS opamp design by employing the current buffer compensation strategy. The designed low power opamp produces an open loop gain above 78 dB, an improved gain-bandwidth product (GBW) 5.82 MHz with an adequate pahse margin of 63.9° in 0.35 μm CMOS technology. The circuit is operated at the single supply voltage of 3.3V with power dissipation of 144.3 μW and an enhanced offset voltage of only 61.5 μV compare to 318 μV offset in [7].

Low Power Adder Circuit Based on Coupling Technique

Today’s technology is continuously scaling itself, thereby resulting in increasing density of the transistors leading to high power dissipation on the chip. Therefore, we need to reduce this power consumption of these circuits and make them more efficient. In this paper, we have introduced two transistors in the Static Energy Recovery Full adder circuit by twisted coupled technique to achieve the power reduction of the circuit. The circuitry proposed in this paper is intended to be operated at 1 V supply with 0.12 mW on 90 nm CMOS technology.

Design of 2-Bit Vedic Multiplier Using PTL and CMOS Logic

The requirement of a high-speed multiplier is expanding. It is one of the most important hardware blocks in a processing system. A multiplier acts as a high delay block, and it also dissipates a lot of power. An ordinary processor requires more time and resources in multiplication operation. The proposed design of the 2-bit Vedic multiplier has been designed using pass transistor logic. The Vedic multiplier is the fastest, reliable, efficient, and low-power multipliers. By reducing the number of partial products, the delay also decreased and the system becomes faster. The design and the properties of this multiplier have been studied and performed using the Pyxis Schematic software (90 nm), and the power dissipation and delay have been compared with 2-bit multiplier using CMOS logic. The analysis is made for voltage range from 0.8 to 1.5 V.

Iterative Basic Block Pipelining Implementation as Fast Computation Technique

The proposed idea is implementation of a multiplier by using operand decomposition through pipelining so as to do fast computation maximum error reduction (Patricio Bulic et al., A Simple Pipelined Logarithmic Multiplier, IEEE International conference on computer Design, 2010 [1], Mahalingam and Rangantathan, IEEE T Comput, 55(2): 1523–1535, 2006. [2], Mclaren, Preceedings of IEEE International SOC Conference 2003, 53–56, 2003 [3]). Implementing the proposed idea with iterative pipelined architecture with less switching activity and this architecture can be opted where speed and accuracy are preferred over complexity.

Design of low power magnitude comparator

A low power two bit magnitude comparator has been proposed in the present work. The proposed magnitude comparator using the technology of coupling has been compared with the basic comparator circuit. The performance analysis of both the different comparators has been done for power consumption, delay and power delay-product (PDP) with VDD sweep. The simulations are carried on Mentor graphics (ELDO Spice) using 90nm CMOS technology at 1 V supply. The simulation results of the coupled magnitude comparator circuits is in good agreement in terms of power consumption at percentage of 60.26% in greater than function and 56.14% in lesser than f unction and 59.48% in equals to function comparators.

Design and Performance Analysis of Bowtie-Shaped Slotted Rectangular Patch Antenna for Terahertz (THz) Applications

The paper comprises the design and simulation of a bowtie-shaped slotted rectangular patch antenna at frequency 1.56 THz for frequency range of 1.2–1.8 THz. GaAs material is used as substrate to achieve better antenna performance. The performance characteristic parameters (return loss, VSWR, gain, and radiation pattern) of proposed design have been portrayed and analyzed to show the performance of antenna. The analyzed results exhibit that the antenna designed shows multiband nature. The overall maximum gain of 7.13 dB is obtained at 1.60 THz and maximum return loss of 32.27 dB is at frequency 1.73 THz. HFSS simulation tool is used to provide platform for simulating the proposed design.

High Speed-Low Power Divide-by-16/17 Dual Modulus Prescaler Using C2MOS

A low power-high speed C2MOS, divide-by-16/17 dual modulus prescaler design is presented. By adopting C2MOS designing technique over simple CMOS implementation, the power dissipation is reduced by 29.48 % and the speed of the circuit is improved by 77 %. It also reduces the chip area as the overall number of transistors used in the proposed circuit is reduced. The circuit is implemented in 0.18 µm CMOS technology. The frequency of operation of the circuit is 10 MHz and it operates at a supply voltage of 2 V.

Multilayer coatings with slotted MDM surface plasmon waveguide for the improvement of sensitivity and transmission with high refractive index material

A MDM (Metal Dielectric Metal) waveguide which is having slotted structure has been studied thoroughly to identify the propagation of surface Plasmon. With the addition of high refractive index material i.e. silicon, The MDM waveguide is analyzed to identify better sensitivity and reflectance. The sensitivity and reflectance of MDM waveguide against the variation of refractive index have been identified with the help of FDTD (Finite Differential Time Domain) method. This geometry not only exhibit high index sensitivity (≈ 19000 nm-RIU⁻¹) but also shows higher transmission (≈ 10 %). Further, we have also investigated the geometry with different dielectric materials (Air, Silicon-di-Oxide). The transmission acquired is of the order Ag — Si — Air — Ag > Ag — Si — Ag> Ag — Si — SiO<inf>2</inf> — Ag for slot MDM structures.

Series computation using Vedic mathematics

This paper emphasize on the Taylors series expansion of sinusoidal, cosine, tangent and exponential functions. The strategy of these series is based on the Vedic mathematics. The impression of designing multiplier based series is embraced from the ancient Indian mathematics found in Wisdom Books `Vedas. Diverse constraints (static and dynamic power, noise margin, delay, LUTs) of three unlike expansions are equated and the results are acquired. VHDL codes are developed and the functionality of these series was tested and executed by using Xilinx Vivado Software (Version: 2014.2). The algorithm used for this is “Urdhva-Tiryagbhyam” one of the sutra of Vedic multiplication. The algorithm was used because it is most competent amid all the sutras.

Low power divide-by-8/9 dual modulus C 2 MOS prescaler

A divide-by-8/9 dual modulus low power C2MOS prescaler circuit design is presented in this paper. The advantage of opting C2MOS designing technique over the simple CMOS implementation is two-fold. Firstly, the chip area is reduced as there is reduction in the total number of transistors used in proposed design. Secondly, the power dissipation is reduced by 44.9%. The circuit operates at 2V voltage supply and is simulated in 0.18 μm technology using Eldo spice simulator of Mentor Graphics.