Anu Mehra

Analysis and comparison of leakage power reduction techniques in CMOS circuits

This paper compares various leakage reduction techniques including Multi-threshold CMOS, Super-Cutoff CMOS, Zigzag, Stack Effect, Input Vector Control, LECTOR, Sleepy Stack, Sleepy Keeper, VCLEARIT, GALEOR, Dual Sleep, Sleepy-Pass Gate and Transistor Gating. The paper elaborately explores the working, comparison and analysis of all these techniques in different CMOS technologies. Leakage Power is analyzed during the standby mode of operation. It has been observed that for a particular circuit leakage depends on CMOS technology as well as leakage reduction technique. In this paper, wide range of results for leakage power reduction techniques of CMOS technologies from 180nm to 45nm is covered which will be helpful for further research in this area.

Gender specific emotion recognition through speech signals

This paper proposes an emotion recognition system which allows recognizing a persons emotional state from speech signal. The aim of proposed solution is to improve the interaction among humans and computers. The emotion recognition system must be capable of recognizing at least six basic emotions (happiness, anger, surprise, disgust, fear, sadness) and the neutral circumstances. The proposed system has two subsystems Gender Recognition (GR) and Emotion Recognition (ER) and also distinguishes a single emotion versus all the others. An appropriate emotion recognition method is applied after extracting features like pitch, energy and MFCC having emotional information. The performance in terms of accuracy is shown in results. The highlight of result is that a prior knowledge about the gender of speaker increases the performance of proposed system. Proposed approach has been implemented by using Naive Bayes method. This is a simple and efficient classification approach. It has easy learning on large speech databases and its accuracy as compared to other approaches is reasonably good. In future this system can be implemented over mobile devices such as smart phones.

Automatic brain tumor segmentation and extraction in MR images

A brain tumor or intracranial neoplasm is formed when abnormal cells get accumulated within the brain. These cells multiply in an uncontrolled manner and damage the brain tissues. Magnetic Resonance Imaging (MRI) scans are commonly used to diagnose brain tumors. However, segmenting and detecting the brain tumor manually is a tedious task for the radiologists. Hence, there is a need for automatic systems which yield accurate results. In this paper, a fully automatic method is introduced to detect brain tumors. The proposed method consists of five stages, viz., Image Acquisition, Preprocessing, Segmentation using Fuzzy C Means technique, Tumor Extraction and Evaluation. Tumor extraction is carried out by using Area and Circularity as a criteria. The results are finally verified by comparing them with the manually segmented Ground Truth. Dice coefficient is also calculated and the average dice coefficient value obtained was 0.729.

Video authentication in digital forensic

The large amount of video content is being transmitted over internet and other channels. With the help of existing multimedia editing tools one can easily change the content of data which lead to lose the authenticity of the information. Thus, it becomes necessary to develop different methods by which the authenticity of the videos can be confirmed. In the past researchers have proposed several methods for authentication of videos. This paper presents an algorithm that is divided in two parts: computing the repeated frames by processing the image pixels to produce a frame-by-frame motion energy time and computing the tampering attack and its location with the help of the Support Vector Machine. This helps to predict whether the given video has been tampered or not.

Brain Tumor Segmentation in Glioma Images Using Multimodal MR Imagery

In this paper, mutlimodal approach has been used for segmenting Tumor core in MRI images using T1-Contrast enhanced, T2-weighted, and FLAIR imaging modalities. Segmentation techniques working on single modality fails to segment brain tumor where the contrast in MR images is low or when sufficient disparity is not present in the intensity of tumor and background region. The proposed method overcome above stated problems by fusing the images of three modalities to form one image. The entire process is divided into five stages: Image Acquisition, Preprocessing, Segmentation, Tumor Extraction, and Evaluation. Two separate segmentation algorithms, Fuzzy C Means and K Means have been used. The results were evaluated using manually segmented Ground Truth. The average Dice accuracy for 18 real tumors (including 12 high grade Glioma and 06 low grade Glioma) is 86 % using Fuzzy C Means as well as K Means. Hence, the proposed method is highly efficient in segmenting tumor core.

Hardware efficient AES for image processing with high throughput

Nowdays, image processing is applied to send an enhanced image in all applications including forensics, robotics, military communications. However, these applications have a additional overhead of image security. AES is one of the high speed technique which is used widely against various attacking techniques inspite of its high computational complexity. In this paper we propose the novel implementation of AES(Advance encryption standard) algorithm with reduced coding complexity and enhanced throughput by parallel processing of the key expansion technique. In addition, proposed approach also reduces the hardware required for implementation of AES. Algorithm is implemented on Xilinx virtex-6 using Questasim 10.0 b and further the encryption and decryption of image is simulated in MATLAB 2011a.

Slew rate and delay optimization of sense amplifier using tradeoff between supply voltage and threshold

Output of SRAM memory circuit is very small i.e. in few milli volts. While reading logic 1 sometimes it is read as logic 0. Due to this malfunctioning of circuit, problem of hazards occur. To overcome this problem we use sense amplifiers. The work of sense amplifier is to sense low power signal from bit line of SRAM memory circuit and amplify the small voltage swing to recognizable logic levels so that data can be interpreted clearly by logic outside the memory. Here we have reduced the delay of the sense amplifier by optimizing the supply voltage i.e. VDD. For this purpose tradeoff between delays, VDD and offset voltage has been done. We have examined the results using IC flow tool.

Low Power Adder Circuit Based on Coupling Technique

Today’s technology is continuously scaling itself, thereby resulting in increasing density of the transistors leading to high power dissipation on the chip. Therefore, we need to reduce this power consumption of these circuits and make them more efficient. In this paper, we have introduced two transistors in the Static Energy Recovery Full adder circuit by twisted coupled technique to achieve the power reduction of the circuit. The circuitry proposed in this paper is intended to be operated at 1 V supply with 0.12 mW on 90 nm CMOS technology.

Design of 2-Bit Vedic Multiplier Using PTL and CMOS Logic

The requirement of a high-speed multiplier is expanding. It is one of the most important hardware blocks in a processing system. A multiplier acts as a high delay block, and it also dissipates a lot of power. An ordinary processor requires more time and resources in multiplication operation. The proposed design of the 2-bit Vedic multiplier has been designed using pass transistor logic. The Vedic multiplier is the fastest, reliable, efficient, and low-power multipliers. By reducing the number of partial products, the delay also decreased and the system becomes faster. The design and the properties of this multiplier have been studied and performed using the Pyxis Schematic software (90 nm), and the power dissipation and delay have been compared with 2-bit multiplier using CMOS logic. The analysis is made for voltage range from 0.8 to 1.5 V.

Design and Implementation of a 32-Bit Incrementer-Based Program Counter

The paper presents the design and implementation of a 32-bit program counter that has been used in DLX-RISC processor which uses Tomasulo Algorithm for out of order execution and a 32-bit program counter based on incrementer logic that was self designed on Virtex-7 FPGA board. The results for power, delay, and area were compared in order to obtain optimal results for the program counter. The power delay product (PDP) of the program counter design based on incrementer logic was found to be 94.4% less than that of the program counter used in DLX-RISC processor. Thereby, the improvised program counter enhances the overall performance of any processor it is used in as the power and delay have been substantially reduced in the proposed design. The designs are simulated and synthesized on Xilinx Vivado 2015.4 using VHDL and are implemented on Virtex-7 FPGA.