Sadasivan Shankar

Die Stacking (3D) Microarchitecture

3D die stacking is an exciting new technology that increases transistor density by vertically integrating two or more die with a dense, high-speed interface. The result of 3D die stacking is a significant reduction of interconnect both within a die and across dies in a system. For instance, blocks within a microprocessor can be placed vertically on multiple die to reduce block to block wire distance, latency, and power. Disparate Si technologies can also be combined in a 3D die stack, such as DRAM stacked on a CPU, resulting in lower power higher BW and lower latency interfaces, without concern for technology integration into a single process flow. 3D has the potential to change processor design constraints by providing substantial power and performance benefits. Despite the promising advantages of 3D, there is significant concern for thermal impact. In this research, we study the performance advantages and thermal challenges of two forms of die stacking: Stacking a large DRAM or SRAM cache on a microprocessor and dividing a traditional micro architecture between two die in a stack

The ultimate CMOS device and beyond

For the past 40 years, relentless focus on Moores Law transistor scaling has delivered ever-improving CMOS transistor density. This paper discusses architectural and materials options which will contribute to the ultimate CMOS device. In addition, the paper reviews device options beyond the ultimate CMOS device.

Three-dimensional wafer-scale copper chemical-mechanical planarization model

Models based on slurry hydrodynamics, mass transport, and reaction kinetics are developed in order to predict the removal rate of copper on a wafer-scale during chemical–mechanical planarization (CMP). The steps in the copper removal model include: mass transport of the oxidizer to the wafer surface; reaction of oxidizer with copper to form a reacted layer; and subsequent removal of the reacted layer by mechanical abrasion. The rates of the chemical reaction and mechanical abrasion steps are described by separate kinetic parameters. For low oxidizer concentrations the chemical step controls the process, while for high concentrations the mechanical step controls. The model shows that mass transport of the oxidizer to the surface controls the removal process at higher removal rates and can cause wafer-scale non-uniformity. Copper CMP experiments with potassium dichromate based slurry are compatible with the proposed surface kinetics steps and showed that the surface kinetics controlled the removal process for this slurry. 2002 Elsevier Science B.V. All rights reserved.

A finite element model of electromigration induced void nucleation, growth and evolution in interconnects

We describe a two-dimensional finite element method designed to model the nucleation, growth and evolution of voids in polycrystalline interconnects. Our computations extend earlier models by accounting in detail for the effects of grain boundaries and interfaces in the solid. In particular, the model includes the effects grain boundary sliding, grain boundary diffusion, grain boundary migration and surface diffusion, as well as elastic deformation and electric current flow within the grains themselves. Front tracking and adaptive mesh generation are used to follow changes in the grain structure and void shape. The method is used to solve representative boundary value problems to illustrate its capabilities.

A FEM/VOF hybrid formulation for underfill encapsulation modeling

Abstract In this paper we present large-scale numerical models for underfill encapsulation processes. The numerical formulation consists of the finite element method coupled with the volume of fluid technique and is based on generalized Hele–Shaw equations. The material behavior is modeled using rheologic kinetic models to predict material bulk properties (i.e. viscosity) and reactions models during the curing process (i.e. gel time). Some simulation examples are presented that demonstrate the applicability of the models to the underfill encapsulation process.

Numerical simulations and experimental measurements of stress relaxation by interface diffusion in a patterned copper interconnect structure

We describe a series of experiments and numerical simulations that were designed to determine the rate of stress-driven diffusion along interfaces in a damascene copper interconnect structure. Wafer curvature experiments were used to measure the rate of stress relaxation in an array of parallel damascene copper lines, which were encapsulated in a dielectric, and passivated with an overlayer of silicon nitride or silicon carbide. The stress relaxation was found to depend strongly on the choice of passivation. Three-dimensional finite element simulations were used to model the experiments, and showed that this behavior is caused by changes in the diffusivity of the interface between the copper lines and the passivation. By fitting the predicted stress relaxation rates to experimental measurements, we have identified the interfaces that contribute to stress relaxation in the structure, and have estimated values for their diffusion coefficients.

First-principles investigations of the dielectric properties of crystalline and amorphous Si3N4 thin films

We have investigated the dielectric properties of silicon nitride thin films with thickness below 6 nm, by using density functional theory calculations. We find a substantial decrease in the static dielectric constant of crystalline films, as their size is reduced. The variation in the response in proximity of the surface plays a key role in the observed decrease. In addition, amorphization of the films may bring further reduction of both the static and optical dielectric constants.

Band offsets and dielectric properties of the amorphous Si3N4/Si(100) interface: A first-principles study

By combining classical and ab-initio simulations, we generated a structural model of an amorphous silicon nitride/silicon(100) interface and we investigated its electronic and dielectric properties from first principles. We computed the valence band offset using many-body perturbation theory, within the GW approximation, and we found results in good agreement with experiments. Based on the computed local band edges and dielectric constants, we estimate that bulk properties are recovered for nitride films with thickness larger than 6–7 A.

Concurrent simulation of neutral flow in the GEC reference cell

This paper describes computational techniques for concurrent Direct Simulation Monte Carlo (DSMC) of neutral flow inside three-dimensional plasma reactors. These techniques are designed to reduce the overall time to obtain realistic three-dimensional results. A simulation problem is first defined by automatically generating a tetrahedral grid. This grid is statically partitioned in order to achieve scalable memory utilization. Parallel algorithms allow high-performance multicomputer architectures to be leveraged to reduce simulation time. Adaptive gridding techniques are employed to maintain the desired accuracy in the presence of dynamic flow variations. Load balancing algorithms, based on heat diffusion, are used to maximize efficiency. Finally, automatic granularity control is used to ensure appropriate granularity for load balancing and for maximum processor utilization. Simulation results are presented for a simulation of the GEC reference cell in a flow configuration of industrial relevance. Performance results are presented for large-scale multicomputers, symmetric multiprocessors and networks of PCs. Copyright

A three-dimensional model of electromigration and stress induced void nucleation in interconnect structures

A three-dimensional finite element method is developed to predict the critical conditions necessary to nucleate electromigration or stress induced voids in interconnects. Our approach is to model interfaces using a modified cohesive zone, which permits the interfaces to separate at a critical stress, and also accounts for mass transport along the interfaces. A simple boundary value problem is solved to verify the numerical procedure. The method is then used to simulate the nucleation and initial growth of voids in a realistic interconnect test structure. Predicted void nucleation sites are in good agreement with experimental observations. In addition, modeling analysis is also consistent with qualitative effects of geometric and material parameters such as the line length, cap layer and passivation material on critical times to nucleate voids.