Safwat G. Zaky

Fingerprint identification using graph matching

Abstract A new algorithm for automated fingerprint encoding and matching is presented. The algorithm is intended to be insensitive to imperfections introduced during fingerprint registration, such as noise, distortion and displacement. A fingerprint is represented in the form of a graph whose nodes correspond to ridges in the print. Edges of the graph connect nodes that represent neighboring or intersecting ridges. Hence the graph structure captures the topological relationships within the fingerprint. The algorithm has been implemented and tested using a library of real-life fingerprint images.

Robust sound localization using multi-source audiovisual information fusion

Abstract This paper illustrates the synergic advantages of a multi-modal sound localization system utilizing two cameras and a 3-element microphone array. The two cameras were used as part of a stereo feature-detection based visual object localization system, while the microphones were combined to produce a sound localization system incorporating a temporal power fusion (TPF) algorithm. The cameras and microphones were integrated using spatial likelihood functions (SLFs), which greatly simplifies the integration process. Test results show a significant improvement in the integrated vision and sound localization (IVSL) systems ability over that of the stand-alone microphone-array based sound localization system to accurately localize sound sources in low signal to noise situations. The IVSL system maintained an average error of 15 cm at signal-to-noise ratios as low as 0.5 dB.

EMI effects and timing design for increased reliability in digital systems

The failure modes of digital circuits subjected to low levels of electromagnetic interference (EMI) are examined. While low-level EMI will not cause static failures (false switching), it may cause dynamic failures by changing the propagation delays of critical signals. A parameter called delay margin is introduced to define the maximum allowable changes in propagation delay under which the circuit will continue to operate reliably. Experimental results are reported in which circuit immunity to EMI is shown to increase significantly when the delay margin is maximized. It is also shown that delay-insensitive circuits have infinite delay margins and are therefore immune to low-level EMI. It was observed experimentally that an oscillating loop subjected to EMI can become phase locked to the frequency of the interference. The second part of the paper describes a synchronization scheme that takes advantage of this phenomenon. The proposed scheme can be used to reduce errors due to synchronizer metastability on communication links between synchronous and asynchronous systems. A reference signal derived from the clock of the synchronous system is injected into a handshake loop, causing the data transfer rate to be locked to a subharmonic of the clock frequency. Both simulation and experimental results are given, showing that stable operation can be achieved over a wide range of parameters.

Communication performance in multiple-bus systems

A simple queueing model is presented for studying the effect of multiple-bus interconnection networks on the performance of asynchronous multiprocessor systems. The proposed model is suitable for systems in which each processor has a local memory and is thus able to continue processing while waiting for a response from the global memory. An approximate, closed-form solution is given that is simple and easy to use for any number of processors, buses, or memory modules and for arbitrary memory block size. The model is used to study the access time of the global memory as a function of the number of buses for different local-memory/global-memory traffic rates. >

EMI-induced failures in crystal oscillators

An electromagnetic interference (EMI) induced failure mode pertaining to crystal-based voltage-controlled oscillators (VCO) has been studied. The failure consists of a transition to a frequency of oscillation that differs from the crystals fundamental resonant frequency, when the circuit is temporarily exposed to continuous or pulsed radio-frequency electromagnetic fields. The new state persists even after the EMI source is removed and leads to hang-up in digital systems. This mode transition has been observed experimentally. Its essential properties have been predicted theoretically and simulated numerically, using simplified oscillator models. The likelihood of observing such a failure in a noisy electromagnetic environment is assessed with respect to the radiated susceptibility levels given in MIL-STD-461B. >

On the prediction of digital circuit susceptibility to radiated EMI

The effects of radiated radio-frequency interference (RFI) on the operation of digital systems are studied by simulating the response of simple logic circuits to incident plane waves. The simulation is accomplished by combining a linear electromagnetic moment-method model of the wire structure with a nonlinear circuit model of the solid-state components. The complete model is analyzed in the linear and nonlinear regimes as an example. It is shown how a circuit simulator, such as SPICE, can be used in the analysis of an arbitrary wire network loaded with logic circuits, by the process of representing the linear wire network as a lumped-element N-port /spl pi/ network and interfacing it to the nonlinear circuit simulator. Examples are given that demonstrate the occurrence of both static and dynamic failures under various RFI-field excitations and wire structure geometries. The prediction methods presented in this paper, can be used by EMC engineers to assess the likelihood of failures in RFI-exposed digital systems,.

Prediction of delays induced by in-band RFI in CMOS inverters

Delays induced by radio frequency interference (RFI) in CMOS inverters are measured under radiated and capacitively coupled interference. Experimental and theoretical investigations of the effects of the RFI coupling mode (capacitive versus inductive) on the amount of induced delay are presented and a worst-case coupling mode is identified. A formula to predict delays caused by in-band low-level RFI in CMOS inverters is introduced. This formula uses experimentally determined parameters which are dependent on the coupling mode. The change in delay is computed as a function of the induced voltage disturbance, which in turn can be computed from the incident field using linear frequency-domain analysis. The formula accounts for the dependence of the induced delay on the phase and amplitude of the RFI signal as well as on the slew rate of the logic transitions. A delay growth phenomenon in a string of inverters is identified and characterized. A correction to the delay prediction formula is proposed in order to take this growth into account in worst-case predictions. >

Algorithmic synthesis of MVL functions for CCD implementation

Algorithms for synthesis of four-valued one- and two-variable functions for CCD (charge coupled device) implementation are proposed. One-variable synthesis is based on the observation that the cost of a realization of a function f(x) increases in the presence of breaks, or negative transitions, in the value of f as x increases. The function is decomposed to minimize the number of such transitions. Two-variable functions are synthesized as a sum of products of literals, taking advantage of literals that are easily implemented in CCD technology. It is concluded that the proposed algorithms perform better than those published previously. >

Sre—a syntax recognizing editor

This paper presents a syntax‐directed editor dubbed SRE, for syntax recognizing editor. Unlike other syntax‐directed editors, SRE enables the user to edit programs with nearly the same natural and unrestrictive ease as a conventional text editor. In addition, it helps identify syntax errors and many typing errors before leaving the editor and attempting to compile a program. Programs are also formatted during entry, thereby providing immediate visual feedback of the recognized structure. The editor replaces the scanner/parser pass of a conventional compiler and thus reduces compilation time substantially.

TORNET: A local area network

TORNET is an experimental local area computer network presently being designed and built in the Computer Group Laboratory of the Department of Electrical Engineering at the University of Toronto. The network consists of a number of local rings, each attached to a central ring. The local rings employ a variation on the slotted-ring format that uses a limited insertion technique to achieve reasonable response times for character traffic among many devices and small computers. Two fixed-length packet formats (one byte or 128 bytes of data) are used on the local rings. Only the longer format is used on the central ring which generally provides record level access to shared specialized equipment. The main objective in the local ring design is a low-cost port for inexpensive terminals, sensors, etc. The paper concentrates on the functional characteristics of the local rings, including delay-throughput comparisons with other well-known ring schemes.