Wayne M. Loucks

Effects of the checkpoint interval on time and space in time warp

Optimistically synchronized parallel discrete-event simulation is based on the use of communicating sequential processes. Optimistic synchronization means that the processes proceed under the assumption that a synchronized execution schedule is fortuitous. Periodic checkpointing of the state of a process allows the process to roll back to an earlier state when synchronization errors are detected. This article examines the effects of varying the checkpoint interval on the execution time and memory space needed to perform a parallel simulation. The empirical results presented in this article were obtained from the simulation of closed stochastic queuing networks with several different topologies. Various intraprocessor process-scheduling algorithms and both lazy and aggressive cancellation strategies are considered. The empirical results are compared with analytical formulae predicting time-optimal checkpoint intervals. Two modes of operation, throttling and thrashing, have been noted and their effect examined. As the checkpoint interval is increased from one, there is a throttling effect among processes on the same processor, which improves performance. When the checkpoint interval is made too large, there is a thrashing effect caused by interaction between processes on different processors. It is shown that the time-optimal and space-optimal checkpoint intervals are not the same. Furthermore, a checkpoint interval that is too small affects space adversely more than time, whereas, a checkpoint interval that is too large affects time adversely more than space.

A heterogeneous environment for hardware/software cosimulation

A heterogeneous environment for hardware/software cosimulation is described. This environment permits a portion of an applications subsystems to be simulated using reconfigurable hardware while the remainder of the subsystems are simulated using software. An Aptix FPCB populated with Xilinx FPGAs serves as the hardware simulation platform while an IBM-compatible PC serves as the software simulation platform. The two platforms are connected using an Altera reconfigurable logic board which allows the development of a high-speed interface for communication. This paper focuses on the difficulties associated with designing and interfacing simulation entities in this heterogeneous environment. Strategies for designing hardware and software simulation entities are introduced. These strategies reduce the impact of size and performance constraints imposed by the cosimulation environment while addressing the issues of time management and synchronization. A simple queueing application is used to illustrate a design methodology which incorporates these design strategies.

Memory management techniques for Time Warp on a distributed memory machine

This paper examines memory management issues associated with Time Warp synchronized parallel simulation on distributed memory machines. The paper begins with a summary of the techniques which have been previously proposed for memory management on various parallel processor memory structures. It then concentrates the discussion on parallel simulation executing on a distributed memory computer—a system comprised of separate computers, interconnected by a communications network. An important characteristic of the software developed for such systems is the fact that the dynamic memory is allocated from a pool of memory that is shared by all of the processes at a given processor. This paper presents a new memory management protocol, pruneback, which recovers space by discarding previous states. This is different from all previous schemes such as artificial rollback and cancelback which recover memory space by causing one or more logical processes to roll back to an earlier simulation time. The paper includes an empirical study of a parallel simulation of a closed stochastic queueing network showing the relationship between simulation execution time and amount of memory available. The results indicate that using pruneback is significantly more effective than artificial rollback (adapted for a distributed memory computer) for this problem. In the study, varying the memory limits over a 2:1 range resulted in a 1:2 change in artificial rollback execution time and almost no change in pruneback execution time.

High performance parallel logic simulations on a network of workstations

An approach for high performance parallel logic simulation on a local area network of workstation computers is discussed in this paper. The single, shared transmission medium often found in such networks places limitations on parallel execution, hence a reduction in the frequency of synchronization is pursued by combining a circuit partitioning methodology with a specific synchronization constraint. A consequence of the partitioning methodology is replication of objects between blocks of a partition. A partitioning procedure based on iterative improvement is described for reducing replication while preserving load balance. Two interprocessor synchronization techniques for parallel simulation are studied: conservative and optimistic synchronization. Experiments conducted on three large sequential circuits indicate that reasonable speedup is achievable for well-balanced partitions, and that optimistic synchronization provides a modest improvement in performance over conservative synchronization.

Implementation of a dynamic address assignment protocol in a local area network

Abstract This paper describes the implementation of a dynamic address assignment protocol (DAAP) on a prototype local area network. A DAAP permits the use of shorter addresses on each packet, which can lead to reduced overhead on networks that support short packets. The protocol described can be applied to any network which permits one station to be distinguished from a set of several stations using the same address. In a network using dynamic addresses a station may arbitrarily use a wrong address; the ensuing problems are discussed.

A hardware/software kernel for system on chip designs

As part of the SoC design process, the application is partitioned between implementation in hardware and implementation in software. While it is customarily the application that is subject to partitioning, it is also possible to partition the software kernel. In this paper, a uniprocessor real-time kernel that implements the Earliest Deadline First (EDF) scheduling policy is partitioned. It is partitioned by moving the EDF scheduler into a coprocessor. The coprocessor size and performance are analyzed. A metric is then proposed that measures a coprocessors impact on application feasibility. This metric permits a unified comparison of kernel coprocessors and application coprocessors during design partitioning.

On a parallel partitioning technique for use with conservative parallel simulation

The major goal of this work has been to develop an implementation of a parallel partitioning algorithm which is suitable for use in a conservatively synchronized Parallel Discrete Event Simulation (PDES) environment. Effective partitioning is essential for performance and capacity consideration, for any PDES problem. The performance of the partitioning algorithm is very important, to the overall simulation performance. There are two possible approaches to improve performance for the partitioning step: algorithm modifications; and parallelize the partitioning algorithm (Fiduccia and Mattheyses, 1982) is developed. The basic algorithm has been modified, first for parallel execution with a similar quality of final partition; and then further modified to increase the parallelism of the algorithm, at the expense of partition quality.

Monitoring the performance of a Web service

This paper describes a conceptual framework for building a software tool that can be used to record the behavior of a Web service. The objective here is to facilitate the building of Web monitoring tools that are flexible, portable, and easy to use. An example implementation using the framework is described. Some measurements provided by the example implementation are also presented.

Using split event sets to form and schedule event combinations in discrete event simulation

Examines the operational characteristics of event set implementations in the presence of a large number of scheduled events. The authors examine a technique to reduce the number of items (i.e., events) to be scheduled by combining all the events to be processed by the same part of the simulation (referred to as a logical process) at the same simulation time. While fewer items need to be scheduled as a result of the formation of these event combinations in existing unified event set implementations, the scheduling must be done by both event time and the identity of the logical process which is to process the event. To address the complexity of this two-component priority, the authors introduce and examine several split event set implementations as schedulers. Empirical performance comparisons between unified and split implementations using closed queuing network and other simulations demonstrate the advantage of split implementations for large event sets.<<ETX>>

A Colliding Puck Simulator for Computational RAM

A Colliding Puck Simulator (CPS) was written for Computational RAM (C/spl middot/RAM), a massively parallel processor-in-memory SIMD architecture. Comparing simulated C/spl middot/RAM execution time with measured workstation execution time, significant speed up is obtained when using up to 800 processor elements.