Salvatore Bonafede

Printing-based assembly of quadruple-junction four-terminal microscale solar cells and their use in high-efficiency modules

Expenses associated with shipping, installation, land, regulatory compliance and on-going maintenance and operations of utility-scale photovoltaics can be significantly reduced by increasing the power conversion efficiency of solar modules through improved materials, device designs and strategies for light management. Single-junction cells have performance constraints defined by their Shockley-Queisser limits. Multi-junction cells can achieve higher efficiencies, but epitaxial and current matching requirements between the single junctions in the devices hinder progress. Mechanical stacking of independent multi-junction cells circumvents these disadvantages. Here we present a fabrication approach for the realization of mechanically assembled multi-junction cells using materials and techniques compatible with large-scale manufacturing. The strategy involves printing-based stacking of microscale solar cells, sol-gel processes for interlayers with advanced optical, electrical and thermal properties, together with unusual packaging techniques, electrical matching networks, and compact ultrahigh-concentration optics. We demonstrate quadruple-junction, four-terminal solar cells with measured efficiencies of 43.9% at concentrations exceeding 1,000 suns, and modules with efficiencies of 36.5%.

Fully integrated AC coupled interconnect using buried bumps

Demonstrated is the fully integrated chip and package technology proposed in ACCI. ACCI provides power and ground distribution by using a buried solder bump, and data transmission through capacitors formed between the chip and package.

Fully Integrated AC Coupled Interconnect Using Buried Bumps

Presented is the complete demonstration of an assembled system using AC coupled interconnect (ACCI) and buried solder bumps. In this system, noncontacting input/output (I/O) are created by using half-capacitor plates on both a chip and a substrate, while buried solder bumps are used to provide power/ground distribution and physical alignment of the coupling plates. ACCI using buried bumps is a technology that provides a manufacturable solution for noncontacting I/O signaling by integrating high-density, low inductance power/ground distribution with high-density, high-speed I/O. The demonstration system shows two channels operating simultaneously at 2.5 Gb/s/channel with a bit error rate less than 10-12, across 5.6 cm of transmission line on a multichip module (MCM). Simple transceiver circuits were designed and fabricated in a 0.35 -mum complementary metal-oxide-semiconductor (CMOS) technology, and for PRBS-127 data at 2.5 Gb/s transmit and receive circuits consumed 10.3 mW and 15.0 mW, respectively. This work illustrates the increasing importance of chip and package co-design for high-performance systems.

Pressure activated interconnection of micro transfer printed components

Micro transfer printing and other forms of micro assembly deterministically produce heterogeneously integrated systems of miniaturized components on non-native substrates. Most micro assembled systems include electrical interconnections to the miniaturized components, typically accomplished by metal wires formed on the non-native substrate after the assembly operation. An alternative scheme establishing interconnections during the assembly operation is a cost-effective manufacturing method for producing heterogeneous microsystems, and facilitates the repair of integrated microsystems, such as displays, by ex post facto addition of components to correct defects after system-level tests. This letter describes pressure-concentrating conductor structures formed on silicon (1 0 0) wafers to establish connections to preexisting conductive traces on glass and plastic substrates during micro transfer printing with an elastomer stamp. The pressure concentrators penetrate a polymer layer to form the connection, and...

Miniaturized LEDs for flat-panel displays

Inorganic light emitting diodes (LEDs) serve as bright pixel-level emitters in displays, from indoor/outdoor video walls with pixel sizes ranging from one to thirty millimeters to micro displays with more than one thousand pixels per inch. Pixel sizes that fall between those ranges, roughly 50 to 500 microns, are some of the most commercially significant ones, including flat panel displays used in smart phones, tablets, and televisions. Flat panel displays that use inorganic LEDs as pixel level emitters (μILED displays) can offer levels of brightness, transparency, and functionality that are difficult to achieve with other flat panel technologies. Cost-effective production of μILED displays requires techniques for precisely arranging sparse arrays of extremely miniaturized devices on a panel substrate, such as transfer printing with an elastomer stamp. Here we present lab-scale demonstrations of transfer printed μILED displays and the processes used to make them. Demonstrations include passive matrix μILED displays that use conventional off-the shelf drive ASICs and active matrix μILED displays that use miniaturized pixel-level control circuits from CMOS wafers. We present a discussion of key considerations in the design and fabrication of highly miniaturized emitters for μILED displays.

Integration of GaN HEMTs onto Silicon CMOS by micro Transfer Printing

Integration of GaN high voltage transistors into Silicon CMOS could combine superior electrical parameters of GaN HEMTs and the huge logic functionality of Silicon CMOS. Several issues of a monolithic integration of GaN devices into CMOS like material mismatch and thermal budgets can be overcome by heterogeneous integration by micro Transfer Printing. Results of first printing experiments with small GaN on Si HEMTs are presented.

On‐Sun Performance of a Novel Microcell Based HCPV System Located in the Southwest US

Semprius has developed a novel microcell based, highly scalable HCPV module that addresses performance, cost and reliability requirements for utility scale solar installations. Semprius has fabricated dual junction cell based engineering prototype modules with 1000X concentration based on this technology. A 1 kW HCPV system using these modules was installed in Tucson to validate the technology and acquire on‐sun data. Eight months of on‐sun results from this system are presented.

Miniature Heterogeneous Fan-Out Packages for High-Performance, Large-Format Systems

High-throughput assembly of miniature wafer-fabricated packages onto panel substrates provides a manufacturing framework for high-performance multi-functional displays and other large-format systems. Control circuits, light emitters, sensors, and other micro-components formed in high-density arrays on wafers use a variety of processes and materials that do not easily translate to large-format panel processing. Systems assembled from some or all of those components can therefore exhibit combinations of properties and performance characteristics that are difficult to achieve by panel processes only. Here, we demonstrate hierarchical assembly strategies for fabricating high-performance systems using elastomer stamp micro-transfer-printing. In this work, red, green and blue microscale inorganic LEDs (µILEDs) are fabricated on their respective native wafer substrates and then assembled onto non-native intermediate silicon wafers. The intermediate silicon wafer, populated with heterogeneous µILEDs, then undergoes conventional wafer-level processes, such a dielectric depositions and thin-film metallization, to form miniature fan-out packages. Here, we will demonstrate three heterogeneous µILEDs integrated within a 75 µm × 35 µm fan-out package. We will present how this microscale package can be undercut and then micro-transfer-printed directly onto large-format application substrates. The print-compatible packages also include sharp pressure-concentrating conductor structures which allow the heterogeneous fan-out packages to be electrically interconnected to large-format substrates during the printing operation. We will present functional µILED displays that have been fabricated using these assembly techniques. We will report on the benefits of using intermediate packaging substrates for manufacturing of high-performance large-format systems, such as displays. We will also demonstrate strategies for repairing large multi-functional systems.

Pressure-Activated Electrical Interconnection During Micro-Transfer-Printing

Sharp electrically conductive structures integrated into micro-transfer-print compatible components provide an approach to forming electrically interconnected systems during the assembly procedure. Silicon micromachining techniques are used to fabricate print-compatible components with integrated, electrically conductive, pressure-concentrating structures. The geometry of the structures allow them to penetrate a polymer receiving layer during the elastomer stamp printing operation, and reflow of the polymer following the transfer completes the electrical interconnection when capillary action forces the gold-coated pressure-concentrator into a metal landing site. Experimental results and finite element simulations support a discussion of the mechanics of the interconnection.

Scalability and Yield in Elastomer Stamp Micro-Transfer-Printing

Elastomer stamp micro-transfer-printing is a highly scalable method for the assembly of microscale components onto non-native substrates. One of the key value propositions of micro-transfer-printing is that the transfer stamp can be scaled to wafer-dimensions and can transfer tens to thousands of micro-devices in a single step, equating to multiple millions of units per hour. Here, we report on the results of systematically scaling the stamp from 12.8 mm × 12.8 mm to a full 150 mm stamp, capable of transferring all the required devices to a 150 mm receiving wafer in one operation. The 150 mm stamp is designed to transfer more than 80,000 chips in one print cycle. This study was carried out using silicon nitride test vehicles that were specially designed for this project. We will discuss how stamp scaling impacts transfer yield and the implications for ultra-high throughput assembly of micro-devices. In addition, we will explore the capability to transfer very small devices down to 3 µm × 3 µm.