John Wilson

3 gb/s AC coupled chip-to-chip communication using a low swing pulse receiver

A 120-mV/sub ppd/ low swing pulse receiver is presented for AC coupled interconnect (ACCI). Using this receiver, 3Gb/s chip-to-chip communication is demonstrated through a wire-bonded ACCI channel with 150-fF coupling capacitors, across 15-cm FR4 microstrip lines. A test chip was fabricated in TSMC 0.18-/spl mu/m CMOS technology and the driver and pulse receiver dissipate 15-mW power per I/O at 3 Gb/s, with a bit error rate less than 10/sup -12/. First-time demonstration of a flip-chip ACCI is also presented, with both the AC and DC connections successfully integrated between the flipped chip and the multichip module (MCM) substrate by using the buried bump technology. For the flip-chip ACCI, 2.5 Gb/s/channel communication is demonstrated across 5.6 cm of transmission line on a MCM substrate.

Flexible, durable printed electrical circuits

This study investigates the screen printing of transmission lines into a variety of nonwoven substrates using different conductive inks for durable and wearable electronic textile applications. The viscosity of the ink dictated the performance of the printed media during washing trials. The printed inks begin to degrade and display lower conductivity after 25 wash cycles. A method to control the durability of the printed circuits, which includes coating of the printed lines with a meltblown layer, has been developed.

A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling

This paper presents a 4.3 GB/s mobile memory interface that utilizes low power states with rapid transition times to support power efficient signaling over a wide range of effective bandwidths. The fastest power state transition is implemented by a global synchronous clock pause that gates dynamic power consumption without any loss of system state. Extensive use of CMOS circuit topologies, with low static power consumption, provides maximum power savings when the clocks are paused. The memory controller forwards a half bit-rate clock to the memory for synchronous communication, which is similarly paused in the low power state. Thus, dynamic interface power on the memory itself naturally responds to the clock pausing, without any explicit communication from the controller or special low-power state on the memory. Low-swing differential signaling based on a push-pull voltage mode driver results in good signal integrity and power efficiency at peak activity. Test-chips fabricated in a 40 nm low-power CMOS technology achieve 3.3 mW/Gb/s power efficiency at 4.3 GB/s data bandwidth, and support better than 5 mW/Gb/s operation over a range from 0.03 to 4.3 GB/s.

Utility of nonwovens in the production of integrated electrical circuits via printing conductive inks

Abstract This study reports on the printing of conductive inks directly onto nonwovens to produce circuits and embedded systems. The approach adopted applies polymer thick film (PTF) processing technologies directly onto compliant, flexible, nonwoven substrates. The paper reports on the characterization of various PTF conductive inks and printed transmission lines. The performance metrics related to the circuits are impacted by the ink viscosity and by the contact angle of the ink on the surface of the nonwoven structure. These parameters dictate the manner in which the ink is distributed onto and into the substrate. The manner in which ink droplets interact with the surface of the substrate determines the mechanisms responsible for both in-plane flow and through-the-plane flow of the ink.

Performance Impact of Simultaneous Switching Output Noise on Graphic Memory Systems

Simultaneous switching output noise (SSO) in single-ended signaling systems is one of the major performance limiters as data rate scales higher. This paper studies the impact of SSO on high performance graphic memory systems (GDDR3/4) using a systematic approach considering both signal and power integrity simultaneously. Specifically, power distribution network (PDN) and channel models are co-simulated in order to study the impact of SSO noise on channel voltage and timing margin. The reference voltage (VREF) noise is also considered as SSO noise couples to both signal and VREF. A methodology for characterizing the system performance by separating high and medium frequency analysis is demonstrated. The worst case system performance is simulated by varying data patterns to excite either medium (100-300 MHz) or high (GHz) frequency noise. A data bus inversion (DBI) coding has recently introduced in GDDR4 to remedy SSO noise and its effectiveness is also investigated in this paper. Finally, the system performance is compared between 4-layer flip-chip and 2-layer chip-scaled packages.

Buried bump and AC coupled interconnection technology

A novel physical structure, buried solder bumps, is introduced that solves the compliance problems that exist in scaling present area array technologies to ever-higher densities. In this technique, buried bumps provide dc connections between integrated circuits and substrates and ac coupled interconnections provide paths for ac signals across the same interface. This approach requires co-design of packaging and circuits and meets the growing demands for both interconnect density and bandwidth. AC coupled interconnection arrays can be built with pitches for ac signals below 100 /spl mu/m and data rates of 6 Gb/s per I/O. This paper presents the physical and circuit aspects of this work as well as measured results from capacitively-coupled circuits fabricated in Taiwan semiconductor manufacturing Company (TSMC) 0.35-/spl mu/m technology. Simulated results from capacitively-coupled circuits in TSMC 0.18 /spl mu/m are also presented.

Electrical Characterization of Transmission Lines on Nonwoven Textile Substrates

The focus of this paper is the electrical characterization of coplanar waveguide (CPW) transmission lines that are printed onto nonwoven textile substrates using conductive inks, to determine their suitability for wide-band applications, e.g. digital signaling. The conductive ink line characterization tests included the defining of DC and Time-Domain Reflectometry metrics. The transmission line test samples were screen printed onto two different types of nonwoven textile substrates using two different conductive inks, i.e. inks with different viscosities. Tests showed that the variations in the continuity of the transmission lines varied, giving rise to geometrical variations in the CPW structure; and in the characterization of the same.

Driver pre-emphasis techniques for on-chip global buses

By using current-sensing differential buses with driver pre-emphasis techniques, power dissipation is reduced by 26.0%-51.2% and peak current is reduced by 63.8%, compared to conventional repeater insertion techniques, for 10mm long buses in TSMC 0.25/spl mu/m technology. This proposed architecture lowers the worst coupling capacitance to total capacitance ratio to 14.4%. It only requires 7.9% more bus routing area than single-ended designs for a 16-bit bus, and saves all of the repeater placement blockages. To further verify that the driver pre-emphasis techniques can also be applied to voltage-mode single-ended buses, a test chip in TSMC 0.18/spl mu/m technology was fabricated and measured.

A 32-Gb/s On-Chip Bus With Driver Pre-Emphasis Signaling

This paper describes a differential current-mode bus architecture based on driver pre-emphasis for on-chip global interconnects that achieves high-data rates while reducing bus power dissipation and improving signal delay latency. The 16-b bus core fabricated in 0.25-mum complementary metal-oxide-semiconductor (CMOS) technology attains an aggregate signaling data rate of 32 Gb/s over 5-10-mm-long lossy interconnects. With a supply of 2.5 V, 25.5-48.7-mW power dissipation was measured for signal activity above 0.1, equivalent to 0.80-1.52 pJ/b. This work demonstrates a 15.0%-67.5% power reduction over a conventional single-ended voltage-mode static bus while reducing delay latency by 28.3% and peak current by 70%. The proposed bus architecture is robust against crosstalk noise and occupies comparable routing area to a reference static bus design.

A 36Gb/s ACCI Multi-Channel Bus using a Fully Differential Pulse Receiver

A new differential pulse receiver is demonstrated for AC coupled interconnect (ACCI), which enables the highest data rate, at 6Gb/s/channel (36Gb/s aggregate), for capacitively coupled systems using pulse signaling. The system works across FR4 printed circuit board (PCB) interconnect lengths of up to 30cm with coupling capacitors from 95fF to 165fF, while dissipating only 1.97mW/Gbps for the entire differential transceiver (0.83pJ/bit for the transmitter and 1.23pJ/bit for the receiver)