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Featured researches published by Sam-Jong Choi.


Semiconductor Science and Technology | 2006

Capacitance-voltage characterization of Ge-nanocrystal-embedded MOS capacitors with a capping Al2O3 layer

Sam-Jong Choi; Byoungjun Park; Hyun-Suk Kim; Kyoungah Cho; Sangsig Kim

Capacitance versus voltage (C–V) curves of Ge-nanocrystal (NC)-embedded MOS capacitors with and without a single capping Al2O3 layer are characterized in this work. C–V curves of the Ge-NC-embedded MOS capacitor with the Al2O3 layer are counterclockwise in the voltage sweeps, which indicates the presence of charge storages in the Ge NCs by the tunnelling of charge carriers between the Si substrate and the Ge NCs. In contrast, clockwise hysteresis of the C–V curves and leftward shifts of the flat band voltages are observed for the embedded MOS capacitor without the Al2O3 layer. It is suggested here that the observed characteristics of the C–V curves are due to the charge trapping at oxygen vacancies within a SiO2 layer. In addition, the illumination of the white light enhances the lower capacitance part of the C–V hysteresis. The origin for the enhancement is discussed in this paper.


Physical Chemistry Chemical Physics | 2016

Atomic layer deposition of diisopropylaminosilane on WO3(001) and W(110): a density functional theory study

Kyung-Tae Lee; Woo-Jin Lee; Hyo Sug Lee; Jai-Kwang Shin; Ji-Eun Park; Seongsuk Lee; Sam-Jong Choi; Sue-ryeon Kim; Jinseong Kim; Youngseon Shim

The decomposition reactions of the Si precursor, diisopropylaminosilane (DIPAS), on W(110) and hydroxylated WO3(001) surfaces are investigated to elucidate the initial reaction mechanism of the atomic layer deposition (ALD) process using density functional theory (DFT) calculations combined with ab initio molecular dynamics (AIMD) simulations. The decomposition reaction of DIPAS on WO3(001) consists of two steps: Si-N dissociative chemisorption and decomposition of SiH3*. It is found that the Si-N bond cleavage of DIPAS is facile on WO3(001) due to hydrogen bonding between the surface OH group and the N atom of DIPAS. The rate-determining step of DIPAS decomposition on WO3(001) is found to be the Si-H dissociation reaction of the SiH3* reaction intermediate which has an activation barrier of 1.19 eV. On the contrary, sequential Si-H dissociation reactions first occur on W(110) and then the Si-N dissociation reaction of the C5H7NSi* reaction intermediate is found to be the rate-determining step, which has an activation barrier of 1.06 eV. As a result, the final products in the DIPAS decomposition reaction on WO3(001) are Si* and SiH*, whereas Si* atoms remain with carbon impurities on W(110), which imply that the hydroxylated WO3 surface is more efficient for the ALD process.


Advanced Gate Stack, Source/Drain, and Channel Engineering fo Si-Based CMOS 2: New Materials, Processes, and Equipment - 210th Electrochemical Society Meeting | 2006

Electrical Characteristics of Ge-Nanocrystal Embedded MOS Capacitors for Non-Volatile-Memory Application

Sam-Jong Choi; Young Soo Park; Kyoo-chul Cho; Tae-Soo Kang; Tae-Sung Kim; Byoungjun Park; Kyoungah Cho; Sangsig Kim

Germanium nanocrystals (NCs)-embedded silicon dioxide (SiO2) layers on top of Si substrates were prepared using the implantation of 74Ge+ ions into the SiO2 layers and the annealing of the implanted oxide layers. The distribution of Ge NCs embedded inside the SiO2 layers was examined by high resolution transmission electron microscopy, and optical properties of the embedded NCs were characterized by photoluminescence and micro-Raman spectroscopy. Capacitance versus voltage (C-V) measurements of Ge NCs-embedded MOS capacitors with single Al2O3 capping layers were performed in order to study memory characteristics of these MOS capacitors. The C-V curves exhibit large threshold voltage shifts originating from charging effect of the Ge NCs, revealing the possibility that the MOS structure is applicable to Nano Floating Gate Memory (NFGM) devices.


Archive | 2006

Integrated circuit device gate structures having charge storing nano crystals in a metal oxide dielectric layer and methods of forming the same

Sam-Jong Choi; Kyoo-chul Cho; Soo-Yeol Choi; Yong-Kwon Kim; Young-soo Park; Chan-kook In; Hae-Jin Park; Sangsig Kim


Archive | 2009

INTEGRATED CIRCUIT DEVICE GATE STRUCTURES

Sam-Jong Choi; Yong-Kwon Kim; Kyoo-chul Cho; Kyung-Soo Kim; Jae-Ryong Jung; Tae-Soo Kang; Sang-Sig Kim


Archive | 2008

NONVOLATILE MEMORY DEVICES THAT INCLUDE AN INSULATING FILM WITH NANOCRYSTALS EMBEDDED THEREIN AND METHODS OF MANUFACTURING THE SAME

Sam-Jong Choi; Kyoo-chul Cho; Jung-Sik Choi; Heesung Kim; Tae-Soo Kang; Yoon-Hee Lee


Archive | 2008

Method of fabricating semiconductor memory device and semiconductor memory device fabricated by the method

Young-soo Park; Sam-Jong Choi; Kyoo-chul Cho; Tae-Soo Kang


Archive | 2011

3D CMOS Image Sensors, Sensor Systems Including the Same

Young-soo Park; Won-joo Kim; Kyoo-chul Cho; Gi-jung Kim; Sam-Jong Choi


Archive | 2008

Nonvolatile memory cell and manufacturing method thereof

圭 徹 ▲そう▼; Kyoo-chul Cho; Jung-Sik Choi; Sam-Jong Choi; Tae-Soo Kang; Hee Sung Kim; Inki Lee


Archive | 2006

Integrated circuit device gate structures and methods of forming the same

Sam-Jong Choi; Yong-Kwon Kim; Kyoo-chul Cho; Kyung-Soo Kim; Jae-Ryong Jung; Tae-Soo Kang; Sangsig Kim

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