Samad Sheikhaei

A 0.8-V supply bulk-driven operational transconductance amplifier and Gm-C filter in 0.18 µm CMOS process

Summary A low voltage bulk-driven operational transconductance amplifier (OTA) and its application to implement a tunable Gm-C filter are presented. The linearity of the proposed OTA is achieved by nonlinear terms cancelation technique, using two paralleled differential topologies with opposite signs in the third-order harmonic distortion term of the differential output current. The proposed OTA uses 0.8 V supply voltage and consumes 31.2 μW. The proposed OTA shows a total harmonic distortion of better than −40 dB over the tuning range of the transconductance, by applying 800 mVppd sine wave input signal with 1 MHz frequency. The OTA has been used to implement a third-order low-pass Gm-C filter, which can be used for wireless sensor network applications. The filter can operate as the channel select filter and variable gain amplifier, simultaneously. The gain of the filter can be tuned from −1 to 23 dB, which results in power consumptions of 187.2 to 450.6 μW, respectively. The proposed OTA and filter have been simulated in a 0.18 µm CMOS technology. Simulations of process corners and temperature variations are also included in the paper. Copyright

Phase noise reduction in a CMOS LC cross coupled oscillator using a novel tail current noise second harmonic filtering technique

A novel technique for reducing phase noise of LC cross coupled oscillators is proposed, using second harmonic filtering of the tail current noise. Using a LC network in between tail current and switching transistors, second harmonic of the tail current noise is filtered out. The filtering circuit works simultaneously as low pass and band stop filters. Therefore, output phase noise is reduced. Three circuits including basic cross coupled oscillator with tail current, and two cross coupled oscillators with conventional and proposed method of tail current noise second harmonic filtering are designed and simulated in 0.13m CMOS technology, with the same power consumption from 1.2V supply. Simulation results show that for the proposed circuit, at 2GHz frequency and 1MHz offset, phase noise and Figure of Merit (FoM) are 130dBc/Hz and 192.3dB, respectively. Compared to basic and conventional circuits, proposed method presents phase noise improvements of 13dB and 7.5dB, respectively, at the cost of increased die area, due to the filtering inductor. Display Omitted

Design of a direct conversion ultra low power ZigBee receiver RF front-end for wireless sensor networks

This paper describes an ultra low power receiver RF front-end to be utilized for wireless sensor network (WSN) applications. The design of the LV cell (LNA and VCO) that is proposed in this paper is suitable for direct conversion architecture, while the conventional LMV cell (LNA, Mixer, and VCO) is used only in low-IF architectures, due to the prohibitive high flicker noise. A passive mixer is utilized instead of an active mixer and a capacitor is added to block the DC current flowing into the mixer. So, flicker noise corner frequency is reduced to 13.8kHz. The proposed design can be used more easily compared to conventional LMV cell in a low voltage technology, because of the stacking of only two blocks (LNA and VCO), while three blocks of LNA, mixer, and VCO are stacked in the conventional LMV cell. The proposed receiver RF front-end consumes 1mW in 0.18@mm CMOS technology with a 1.2V supply source. NF and IIP3 are 4.7dB and -7dBm, respectively.

Intelligent lighting control with LEDS for smart home

This paper presents intelligent lighting control system for smart home. The AC power source is converted down with an AC to DC switching power supply, then is delivered to some LEDs with an LED driver. This paper proposes two methods of lighting control. In the manual control method, LED is controlled with a PWM signal. In fact, according to the user command, it generates the proper duty cycle in a PWM signal. In the automatic control method, the LED is controlled with a signal generated by the PID control algorithm. In this method, the photocell measures the ambient light level and with reference to the input command by the user, proper PWM signal is generated. Circuit schematics and the implementation details are presented. A laboratory prototype is also designed and tested to verify the feasibility, and the experimental results are demonstrated.

Pseudo-impulse tail current shaping for phase noise reduction in CMOS LC oscillators

Abstract In this paper, a low phase noise oscillator using tail current shaping method is presented. The current shaping is achieved using two paths for current disconnection and current injection, as a result of which, the total tail current is shaped to a sharp and sawtooth waveform, close to an impulse. Each switching transistor is ON only in 22% of an oscillation period, and tail current is mostly supplied to these transistors near the outputs peak points. In those moments, the oscillator sensitivity to noise sources is minimum. The proposed oscillator is designed and simulated in 0.18 μm RF CMOS technology with 1.8 V supply, and using the inductor model offered by the process, with quality factor of 11. Post layout simulations predict an oscillation frequency of 1.65 GHz, and phase noise of −127.7 dBc/Hz at 1 MHz offset, which is 6.3 dB better than that of simple cross coupled oscillator with the same core oscillator power consumption of 2.2 mW. The proposed circuit, however, consumes an extra power of about 1.9 mW for the added current shaping circuits. Compared to conventional tail current shaping technique, the proposed oscillator offers better tail current shaping, and a much higher start-up current and gain, which is desirable.

A 4mW 3-tap 10 Gb/s decision feedback equalizer

A half-rate low-power 3-tap decision feedback equalizer (DFE) was designed in 90-nm CMOS technology. An improved switched-capacitor-based summer architecture is used in the front-end sample-and-hold to speculate the first feedback tap. Other two taps are canceled using current summation technique. Further power consumption reduction is achieved by using sense-amplifier-based slicer and pass-gate multiplexer instead of CML architecture. An accurate characterization of DFE, based on Least Square Estimation and using random sequence, with certain probabilistic characteristics suitable for intended operating conditions, is described. The Proposed 3-tap DFE consumes 4mW from a 1.2V supply when equalizing 10 Gb/s data passed over a 10″ NELCO channel with 15dB of loss at 5 GHz.

A 12.5Gb/s active-inductor based transmitter for I/O applications

This paper presents an improved PMOS-based active inductor circuit suitable for output driver in wireline link transmitters. Wider tuning range and higher inductive impedance in the desired bandwidth with respect to a previous reported topology is achieved using a varactor in the active inductor architecture and modifying the feedback resistor. Using the proposed active inductor, a prototype output driver for a wireline transmitter is designed in a 90nm CMOS technology. To model nonidealities of the active-inductor that affects the transmitter performance, an accurate large-signal, wide-band characterization technique, based on Least Square Estimation is described. Amplification of high frequency components of 10 Gb/s and 12.5 Gb/s transmitted signals over two kinds of NELCO channels using active inductors in the transmitter side, improves SNDR in the receiver side by 3 dB, as compared to the case with no inductor peaking, for the same power consumption. The transmitter circuit consumes 8.4 mW from a 1.2V power supply.

A low phase noise super–harmonic coupling quadrature VCO using an additional double frequency oscillator

Abstract In this paper, using an additional oscillator that operates at twice the main output frequency, super–harmonic coupling is created between two LC cross–coupled oscillators. The additional oscillator output signals are injected into the two main oscillators in a special way, such that in addition to forcing those oscillators to work in quadrature mode, a tail current shaping technique is performed on them, through the same circuit path. As a result, the main oscillators output phase noise is reduced. The second harmonic signals with the help of two additional NMOS transistors shape the gate voltages and consequently the drain current of the tail transistors. The quadrature mode operation of the proposed circuit is mathematically proved and the intrinsic tail current shaping behavior of it is analyzed. The proposed QVCO is designed in a 0.18 μm CMOS technology with a supply voltage of 1.8 V and a total power consumption of 4.4 mW at 2 GHz center frequency with 5.5% tuning rage. Simulation results confirm the proposed quadrature mode operation. It also shows the phase noise of −128.1 dBc/Hz for the proposed QVCO at 1 MHz offset and 1.92 GHz carrier, which is 9.3 dB better than that of the conventional Parallel (P)–QVCO. The maximum phase error for 0.5% I and Q tank capacitor mismatch is 1.47°.

Design and implementation of a tele-examination system

This paper describes a low-cost, reliable and easily used long-distance health monitoring system, named teleexamination system. In this equipment, the patient is examined online in a live communication platform. Personal computers and/or smart phones as the main processing cores of this system are available everywhere and reduce the final cost of the telemedicine systems. In our proposed system, a bidirectional audio-visual connection is established. By means of a few added special devices for monitoring different body parameters, the doctor could listen to patients heart sound as well as measure the body temperature, heart rate, and ECG, and finally prescribe the medicine. This system can be used in many places including, wherever doctors are not available, such as in rural areas, or for disabled people, who are not able to go to a hospital.

A 168µW MICS band transmitter based on injection locking for biomedical sensor nodes

Currently need for ultra low power wireless transmitters in medical applications are inevitable. In this paper a new transmitter for body-worn and implantable sensor nodes is presented. Most of the sensor nodes supply their power using energy harvesting instead of a battery, since the power earned by harvesting is limited, so the average and the peak power consumption of the sensor node must be minimized. transmitter blocks which implemented in sensor nodes are too power consuming. So we propose a new low power Binary Frequency Shift Keying (BFSK) transmitter based on sub-harmonic current mode injection locking, and edge combining technique. A 34MHz reference clock is used and the frequency of reference clock multiplied by 12 for desired carrier frequency. The phase noise of the carrier at 1MHz frequency offset is -110.3dBc, total power consumption is about 168μW. The output carrier frequency is 408MHz. BFSK modulation scheme is used at the frequency much lower than the carrier frequency in order to reduce the power consumption.