Saman Adham

Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study

Recent advances in semiconductor process technology especially interconnects using Through Silicon Vias (TSVs) enable the heterogeneous system integration where dies are implemented in dedicated, optimized process technologies and stacked in a 3D form. TSMC has developed the CoWoS™ (Chip on Wafer on Substrate) process as a design paradigm to assemble silicon interposer-based 3D ICs. To reach quality requirements for volume production, several test challenges related to 3D ICs need to be addressed. This paper describes the test and debug strategy used in designing a CoWoS™ based stacked IC. The 3D design presented in the paper contains three heterogeneous dies (a logic, a DRAM, and a JEDEC Wide-I/O compliant DRAM) stacked on the top of a passive interposer. For passive interposer testing, a novel test methodology called Pretty-Good-Die (PGD) test is presented, while for inter-die test, a novel scalable multi-tower 3D DFT architecture is presented. Silicon results show that most of the test challenges can be solved efficiently if planned properly; and 3D ICs are reality and not a fiction anymore.

A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application

A 1 Tbit/s bandwidth PHY is demonstrated through CoWoS™ platform. Two chips: SOC and embedded DRAM (eDRAM), have been fabricated in TSMC 40 nm CMOS technology and stacked on a silicon interposer chip. 1024 DQ buses operating at 1.1 Gbit/s with VDDQ = 0.3 V are proven between SOC chip and eDRAM chip in experimental results with 1 mm signal trace length on the silicon interposer. A novel timing compensation mechanism is presented to achieve a low-power and small area eDRAM PHY that excludes PLL/DLL but retains good timing margin. Another data sampling alignment training approach is employed to enhance timing robustness. A compact low-swing IO also achieves power efficiency of 0.105 mW/Gbps.

The importance of DFX, a foundry perspective

Silicon foundries are enabling fab-less chip design companies to meet market demand of highly integrated devices as mobile applications are flourishing in recent years. Foundries are also enabling other sectors of the semiconductor industry to provide high performance systems to meet the required bandwidth for mobile applications. Significant investments in the development of advanced technology nodes are made to ensure future demand are met. This makes Fab utilization of high importance. This paper discusses the importance of DFX (DFT, DFM, DFB, DFA) disciplines to accelerating technology bring up and enabling fast customer volume ramp up. We show how basic and advance DFT methodologies are used to design and test special structures to enable fast failure analysis identifying design and manufacturing constraints. We also discuss the role of DFX in failure analysis in improving the design and manufacturing rules.

Design-for-diagnosis: Your safety net in catching design errors in known good dies in CoWoS TM /3D ICs

To meet power, performance and area requirements of modern electronic products, heterogeneous system integration where dies implemented in dedicated, optimized process technologies are stacked together to form a system is inevitable. The use of known-good pre-fabricated dies provides substantial reduction in time-to-market for integrated products. However, as dies from different suppliers using different technologies are used, finding source of design errors or manufacturing defects becomes very challenging if an integrated system fails in production. The system integrator has the onus to include test and diagnosis features that can enable post-silicon debugging. In this paper, we present a silicon diagnosis case study for a TSMC CoWoSTM based heterogeneous 3D chip. We demonstrate how the Design-for-Diagnosis features implemented on the logic die were used to isolate interconnects testing failures. We were not only able to speed up the diagnosis but also able to find the real source of failure, which was a design and modeling issue in one of the 3rd party known-good-die.

A novel DFT architecture for 3DIC test, diagnosis and repair

Three-dimension ICs (3D-ICs) are the current trend due to their improvement in heterogeneous integration, performance, power consumption, silicon area, and form factors. However, the consequent new challenges are interconnects between dies, i.e., Through-Silicon-Vias (TSVs) and micro-bumps (μ-bumps). Therefore, many interconnect test, diagnosis, and repair schemes were proposed, such as double TSVs & double μ-bumps schemes. In this paper a novel DFT technique is presented based on the double resource schemes. Challenges to two-die, multi-tier, and numerous interconnects are handled by proposed testable, diag-nosable, repairable, and scalable element, structure, and flow.