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Dive into the research topics where Sandeep Kumar Goel is active.

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Featured researches published by Sandeep Kumar Goel.


international test conference | 2000

Wrapper design for embedded core test

Erik Jan Marinissen; Sandeep Kumar Goel; Maurice Lousberg

A wrapper is a thin shell around the core, that provides the switching between functional, and core-internal and core-external test modes. Together with a test access mechanism (TAM), the core test wrapper forms the test access infrastructure to embedded reusable cores. Various company-internal as well as industry-wide standardized but scalable wrappers have been proposed. This paper deals with the design of such core test wrappers. It gives a general architecture for wrappers, and describes how a wrapper can be built up from a library of wrapper cells which are selected on basis of the terminal types of the core. We show that the ordering and partitioning of wrapper cells and core-internal scan chains over TAM chains determine the test time of the core. An heuristic approach for the NP-hard problem of partitioning the TAM chain items for minimal test time is presented and its usage is illustrated by means of an example. Finally we sketch how wrapper generation and verification can be automated.


IEEE Design & Test of Computers | 2002

Design for debug: catching design errors in digital chips

Bart Vermeulen; Sandeep Kumar Goel

For large, complex ICs, engineers need efficient techniques for debugging first silicon. The system presented here consists of an on-chip debug infrastructure and supporting debugger software,which interacts with the infrastructure to make the chips features accessible through a serial interface.


international test conference | 2002

Core-based scan architecture for silicon debug

Bart Vermeulen; Tom Waayers; Sandeep Kumar Goel

In this paper, we present a core-based scan architecture for silicon debug, which is currently being standardized within Philips. The reasons behind the core-based debug architecture, together with implementation details, are described. The choices that were made during its development are explained using the experiences gained from two large Philips system chips that each utilize core-based design and test, and scan-based silicon debug. The results of an area-cost evaluation of the presented architecture for these two large system chips are also presented.


design automation conference | 2004

Automatic generation of breakpoint hardware for silicon debug

Bart Vermeulen; Mohammad Zalfany Urfianto; Sandeep Kumar Goel

Scan-based silicon debug is a technique that can be used to help find design errors in prototype silicon more quickly. One part of this technique involves the inclusion of breakpoint modules during the design stage of the chip. This paper focuses on an innovative approach to automatically generate breakpoint modules by means of a breakpoint description language. This language is illustrated using an example, and experimental results are presented that show the efficiency and effectiveness of this new method for generating breakpoint hardware.


design, automation, and test in europe | 2004

Test infrastructure design for the Nexperia/spl trade/ home platform PNX8550 system chip

Sandeep Kumar Goel; Kuoshu Chiu; Erik Jan Marinissen; Toan Nguyen; Steven Oostdijk

Philips has adopted a modular manufacturing test strategy for its SOCs that are part of the Nexperia/spl trade/ home platform. The on-chip infrastructure that enables modular testing consists of wrappers and test access mechanisms (TAMs). Optimizing that infrastructure minimizes the test application time and helps to fit the test data into the ATE vector memory. This paper presents the test architecture design for the chiplet-based PNX8550, the most complex Nexperia/spl trade/ SOC designed to date. Significant savings in test time and TAM wires could be obtained with the help of TR-ARCHITECT, an in-house tool for automated design of SOC test architectures.


vlsi test symposium | 2002

Cluster-based test architecture design for system-on-chip

Sandeep Kumar Goel; Erik Jan Marinissen

A test architecture for an SOC consists of a number of Test Access Mechanisms that connect to wrapped cores. This paper presents a new test architecture, named the TestRail Architecture, that is a hybrid form of the known Daisychain and Distribution Architectures. An important characteristic of the TestRail Architecture is that it allows for efficient testing of both the cores as well as the core-external circuitry. We present two alternative optimization algorithms for the TestRail Architecture, that minimize the total core-internal test time of the cores in the SOC. These algorithms handle both cores with fixed-length and flexible-length scan chains. Experimental results on three industrial benchmark SOCs show that, compared to previous publications, we obtain comparable or better test times at drastically reduced compute times.


international test conference | 2011

Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base

Chun-Chuan Chi; Erik Jan Marinissen; Sandeep Kumar Goel; Cheng-Wen Wu

Through-Silicon Vias (TSVs) enable high-density, low-latency, and low-power interconnects for system chips that consist of multiple dies. In “2.5D” Stacked ICs (2.5D-SICs), multiple dies without TSVs are stacked side-by-side on top of a passive silicon interposer base containing TSVs. In true 3D-SICs, multiple dies containing TSVs themselves are vertically stacked; one or multiple of such stacks are possibly placed on a passive silicon interposer. This paper proposes a post-bond test and design-for-test (DfT) strategy for 2.5D- and 3D-SICs containing a passive silicon interposer base. Functional interconnects in the interposer are reused as much as possible in order to keep the interposer cost low.


design, automation, and test in europe | 2003

Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization

Sandeep Kumar Goel; Erik Jan Marinissen

This paper extends existing SOC test architecture design approaches that minimize required tester vector memory depth and test application time, with the capability to minimize the wire length required by the test architecture. We present a simple, Yet effective wire length cost model for test architectures together with a new test architecture design algorithm that minimizes both test time and wire length. The user specifies the relative weight of the costs of test time versus wire length. In an integrated fashion, the algorithm partitions the total available TAM width over individual TAMs, assigns the modules to these TAMs, and orders the modules within one TAM such that the total cost is minimized. Experimental results on five benchmark SOCs show that we can ()brain savings of up to 86% in wiring costs at the expense of <4% in test time.


vlsi test symposium | 2009

Effective and Efficient Test Pattern Generation for Small Delay Defect

Sandeep Kumar Goel; Narendra Devta-Prasanna; Ritesh P. Turakhia

Testing for small delay defects is critical to guarantee that the manufactured silicon is timing-related defect free and to reduce quality loss associated with delay defects. Commercial solutions available for testing of small delay defects result in very high pattern count and run time. In this paper, we present two effective approaches for generating timing-aware transition fault patterns that target small delay defects. We identify a subset of transition faults that should be targeted by the timing-aware ATPG; while for the rest of the faults, classic non-timing-aware transition fault patterns can be generated. Experimental results for several industrial benchmarks show that the proposed approaches result in up to 75% reduction in test pattern count compared to existing timing-aware ATPG approaches.


international test conference | 2012

DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks

Sergej Deutsch; Brion L. Keller; Vivek Chickermane; Subhasish Mukherjee; Navdeep Sood; Sandeep Kumar Goel; Ji-Jan Chen; Ashok Mehta; Frank Lee; Erik Jan Marinissen

Three-dimensional (3D) die stacking is an emerging integration technology which brings benefits with respect to heterogeneous integration, inter-die interconnect density, performance, and energy efficiency, and component size and yield. In the past, we have described, for logic-on-logic die stacks, a 3D DfT (Design-for-Test) architecture and corresponding automation, based on die-level wrappers. Memory-on-logic stacks are among the first 3D products that will come to the market. Recently, JEDEC has released a standard for stackable Wide-I/O Mobile DRAMs (Dynamic Random Access Memories) which specifies the logic-memory interface. The standard includes boundary scan features in the DRAM memories. In this paper, we leverage and extend the 3D DfT wrapper for logic dies, such that, in conjunction with the boundary scan features in the Wide-I/O DRAM(s) stacked on top of it, testing the logic-memory interconnects is enabled. A dedicated Interconnect ATPG (Automatic Test Pattern Generation) algorithm is used to deliver effective and efficient dedicated test patterns. We have verified our proposed DfT extension on an industrial design and shown that the silicon area cost of the extended wrapper with JEDEC Wide-I/O interconnect test support is negligible.

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