Sambhu Nath Pradhan

Low power finite state machine synthesis using power-gating

Power-gating turns off the power supply of a portion of the circuit completely, resulting in total elimination of power consumption for that part. However, it also necessitates that the sub-circuit to be activated should be charged for some time before its activation. This critical issue can influence the decomposition of a finite state machine (FSM) for its power gated implementation. In this paper we have presented a power-gating method that integrates FSM partitioning with state encoding, thus providing a total solution to the problem of power-aware FSM synthesis. It shows better results, in terms of dynamic and leakage power consumption, compared to the existing techniques reported in the literature.

Integrated Power-Gating and State Assignment for Low Power FSM Synthesis

Power-gating is an effective technique for reducing standby leakage power and dynamic power. In power-gating one can shut off the power supply to sections of logic block while keeping other logic blocks active. However, careful design is required to make power-gating technique effective, otherwise, negative effect of power-gating may overwhelm the potential gain. In this paper we have presented the state partitioning and state encoding strategy targeting low power finite state machine (FSM) decomposition based on genetic algorithmic approach. All the previous works dealt only FSM partitioning but did not consider state encoding together. This is the first ever approach considering FSM partitioning and state encoding together in power-gating technique. Experimental result shows that upto 73% power saving can be done giving small amount of area penalty.

Low Power BDD-based Synthesis Using Dual Rail Static DCVSPG Logic

Binary decision diagrams (BDDs) play an important role in the synthesis, verification, and testing of VLSI circuits. In this paper, we have proposed a new BDD-based synthesis technique using dual rail static differential cascode voltage switch with pass gate (DCVSPG) logic. The method yields around 22% reduction in number of MUX cells. Simulation result using SPICE on 180 nm technology with 1.5 volts supply shows, on an average, 65% reduction in power consumption for frequency ranging up to 1 GHz compared to the result with static CMOS logic. It is envisaged that the proposed approach is useful in realizing low-power circuits

An Autonomous Clock Gating Technique in Finite State Machines Based on Registers Partitioning

Reducing the power dissipation associated with the clock network in a sequential circuit can result in significant dynamic power saving. In this work, an efficient technique of autonomous clock gat...

Reduction of Noise Using Continuously Changing Variable Clock and Clock Gating for IC Chips

The performance of silicon chip depends on the operating voltage of the chip. The chip should be designed using proper power and ground bond pads to minimize the power supply noise. When the chip starts working from the sleep mode, then the sudden rise in current inside the chip causes LdI/dt noise. This noise reduces the power supply voltage, which in turn reduces the operating frequency of the chip. This makes the chip manufacturer to sell products of high-performance chips at a lower operating frequency. In order to ramp this current slowly, an innovative and fundamentally new method is implemented. In this proposed method, we have increased the operating frequency inside the chip slowly (from fmin to fmax) to control the current ramp and at the same time performed clock gating (CG) to minimize noise by suppressing the current drawn by the device. We have applied this concept of variable frequency together with CG in a 3-b up counter to demonstrate that one can construct a design where the clock can be modulated during its functional operation without any functional failure.

Low power and high testable Finite State Machine synthesis

As the density of the VLSI chip increases, the testing and power consumption are becoming major concerns for its use in various applications. To reduce the expense of the VLSI chip design especially for the testability and low power consumption, the optimization has to be considered near the beginning stage of the design such as logic synthesis level. Power and testability issues of FSM (Finite State Machine) during synthesis are considered in this paper. For the FSM circuits at the logic synthesis level synthesis is done for the reduction of both power consumption and increase in testability. To do so during synthesis both the power and fault coverage which is the measure of testability are taken together in the cost function of GA (Genetic Algorithm) and are optimized. Reduction of power dissipation may leads to decrease in fault coverage. So, there is a trade-off between power and fault coverage. This trade-off analysis has been performed and finally after synthesis a circuit that has optimum power and highest fault coverage is obtained.

Power modeling of power gated FSM and its low power realization by simultaneous partitioning and state encoding using genetic algorithm

Partitioning is an effective method for synthesis of low power finite state machines (FSM). To make the partitioning more effective power gating can be applied to turn OFF the inactive sub-machine. During transition from the states of one sub-machine to the states of other sub-machine, the supply voltage is required to be turned OFF for one sub-machine and turned ON for other sub-machine. This adjustment of supply voltage needs some amount of time. Hence, it effects the partitioning of FSMs for its power gated implementation as both the sub-machines are ON during this time. In this paper we have considered this issue by developing a new probabilistic power model of the power-gated design of FSM. As effective partitioning and encoding of FSM decides the power consumption of final power gating implementation, in this paper Genetic Algorithm (GA) has been used to solve this integrated problem of both bi-partitioning and encoding. Experimental results obtained show the effectiveness of the approach in terms of total dynamic power consumption, compared to the technique reported in the literature.

An elitist area-power density trade-off in VLSI floorplan using genetic algorithm

Due to trade-offs between the VLSI circuit parameters, chip suffers from reliability issues. It needs to be optimizing for better performance. Such problems are defined as NP-hard problems. In this paper a heuristic has been developed using genetic algorithm for solving the floorplan problem. The proposed algorithm is an improved floorplan algorithm, for optimizing simultaneously the trade-off parameters area and zonal peak power density. The initial populations are randomly chosen from a superset of large initial population & genetic algorithm is implemented to obtain the best floorplan solution. Randomized selection is taken to make the selection area flexible. The proposed algorithm has been validated with the ISCAS85 benchmark circuits for 65nm and 90nm.

Thermal aware FPRM based AND-XOR network synthesis of logic circuits

With the advent of incorporating increased number of complex logic blocks within a VLSI chip, power-density is increasing. Power-density directly converges into temperature which reduces the yield of the circuit. Adverse affect of power-density reduction is increase in area. So, there is a trade-off between area and power-density. Previous works has been done on the Fixed Polarity Reed-Muller (FPRM) AND-XOR realization for its reduced area or low power realization. In this paper, we present a Genetic Algorithm(GA) based non-exhaustive heuristic to increase the sharing of product terms by selecting the proper polarity of input variables in FPRM expansion and a suitable area and power-density trade-off has been enumerated. Incorporation of the power-density as a fitness constraint in FPRM based optimization for temperature analysis is the first ever effort. The proposed algorithm has been validated with the LGSynth93 benchmark circuit.

A technique for power reduction of CMOS circuit at 65nm technology

The overall power consumption in nano-scaled device has reached an alarming state mainly due to the increasing trend of various leakage components. This escalated power consumption leads to device characteristics breakdown due to hot-spot creation within the integrated Package. As a result, as technology advances overall power dissipation of VLSI circuit needs to be controlled by power-aware design. Here we propose an idea through which we can reduce the overall power consumption by simple modification in the reference circuit. Pre-layout and post-layout simulation of modified circuit shows a significant improvement in power consumption. Power saving has been compared with the existing leakage reduction technique such as transistor stacking. The area and delay overhead for the implementation of the modified structure are very less.