Priyanka Choudhury

Low power and high testable Finite State Machine synthesis

As the density of the VLSI chip increases, the testing and power consumption are becoming major concerns for its use in various applications. To reduce the expense of the VLSI chip design especially for the testability and low power consumption, the optimization has to be considered near the beginning stage of the design such as logic synthesis level. Power and testability issues of FSM (Finite State Machine) during synthesis are considered in this paper. For the FSM circuits at the logic synthesis level synthesis is done for the reduction of both power consumption and increase in testability. To do so during synthesis both the power and fault coverage which is the measure of testability are taken together in the cost function of GA (Genetic Algorithm) and are optimized. Reduction of power dissipation may leads to decrease in fault coverage. So, there is a trade-off between power and fault coverage. This trade-off analysis has been performed and finally after synthesis a circuit that has optimum power and highest fault coverage is obtained.

Power modeling of power gated FSM and its low power realization by simultaneous partitioning and state encoding using genetic algorithm

Partitioning is an effective method for synthesis of low power finite state machines (FSM). To make the partitioning more effective power gating can be applied to turn OFF the inactive sub-machine. During transition from the states of one sub-machine to the states of other sub-machine, the supply voltage is required to be turned OFF for one sub-machine and turned ON for other sub-machine. This adjustment of supply voltage needs some amount of time. Hence, it effects the partitioning of FSMs for its power gated implementation as both the sub-machines are ON during this time. In this paper we have considered this issue by developing a new probabilistic power model of the power-gated design of FSM. As effective partitioning and encoding of FSM decides the power consumption of final power gating implementation, in this paper Genetic Algorithm (GA) has been used to solve this integrated problem of both bi-partitioning and encoding. Experimental results obtained show the effectiveness of the approach in terms of total dynamic power consumption, compared to the technique reported in the literature.

CG-in-PG architecture implementation for power reduction in FSMs

By gating the power supply of the inactive part of the finite state machine (FSM) circuit, total power is reduced but the active part continues to dissipate power. So, there is a possibility of applying clock gating (CG) to the active part of the power-gated FSM. A transition may happen in which the states do not change but output changes. This issue has not been addressed by the conventional CG, so, for reducing the switching of register during CG and to overcome the issue, conventional CG has been modified by splitting the input latch of the FSM circuit. The architecture termed as CG-in-PG is designed in such a way that when one sub-FSM is inactive it adopts power gating (PG) for power reduction and other sub-FSM seeks for possible CG during its active period. So, both the sub-FSM is capable of reducing power either by PG or by CG depending on whether it is in inactive mode or active mode. To the best of our knowledge, this is the first ever approach of applying CG after power-aware genetic algorithm (GA)-based bi-partitioning and encoding of FSM for power-gated design. The synthesis of the proposed design has been implemented in Cadence digital synthesis tool. The results show 36.94% average saving after applying CG-in-PG with respect to only PG.

Hybrid Approach of Within-Clock Power Gating and Normal Power Gating to Reduce Power

Power gating (PG) is used to reduce leakage power by shutting down the power supply of the inactive block of the circuit. PG technique for finite state machine (FSM) is used to reduce not only leakage power but also the switching power of circuit. One FSM is partitioned into two sub-FSMs and encoded for minimizing total power for the power-gated design of the circuit. Depending on the state of the machine, at a time one sub-FSM is power gated by shutting off the power supply. There is a complete eradication of power in power-gated sub-FSM, but another one is in an active mode that continues to dissipate power. There is a scope to reduce leakage in active sub-FSM if the clock period is larger than the critical path delay of the combinational part of this sub-FSM. In this condition, there is a certain portion of the clock period which is idle and in this period PG may be used. The objective of this paper is to reduce power by applying PG at circuit level to the active sub-FSM, whereas, inactive sub-FSM is still power gated. This paper presents a new technique, called WCPG_IN_PG, which reduces the power of active sub-FSM (within the clock period) and power-gated FSM. By varying the frequency, power results are reported for different input combinations.

Power gating architecture implementation inside clock period to reduce power

In today’s nanometre regime of device dimension, leakage power has become comparable to dynamic power. Along with the other leakage reduction techniques, power gating is a technique which is used to reduce standby leakage and dynamic power by shutting down the power supply of the inactive block of the circuit but the active blocks continues to dissipate power. It has been observed that there is a scope of using power gating in active block to reduce run time leakage. If the operating frequency is lower than the maximum operating frequency of the circuit, then within clock period there is a certain portion which is idle and in this period power gating may be applied. This paper concerns about the implementation of power gating in this idle time of the clock. Architecture of this power gating technique designed to work within the clock period termed as ‘within-clock power gating’ (WCPG) for minimising leakage and total power of the sequential circuits during active mode of operation has been proposed in this paper. In this architecture an ISCAS89 benchmark circuit has been implemented. Power results have been reported for different frequencies. Simulation of the implemented architecture in CADENCE VLSI tool at 45 nm technology shows up to 85% saving in leakage and around 10% saving in total power compared to the no power gating at 2.5 MHz frequency.

Transistor level realisation of power gated FSM

Power can be minimised for the power gated finite state machine (FSM) by suitable partitioning and encoding strategy. Power gating architecture designed previously at FSM level is hypothetical one and may not directly be used for practical implementation of power gated circuit in transistor level. Most of the previous works concern about power reduction of combinational parts only. In this work, a new architecture of power gating design which implements sequential circuit in transistor level has been proposed and considers power consumption of combinational as well as sequential parts. The sequential circuits are obtained after concurrent bi-partitioning and encoding of FSM benchmark circuit. Multi-level realisation of two-level PLA circuit has been done. The architecture is designed such that at a time combinational circuits corresponding to one sub-FSM is power gated by shutting-OFF power supply. Power gating technique in this work shows leakage saving of 47% and total power saving of 53.6%.

Design of new high-speed and low-energy dynamic PLA

Programmable logic arrays (PLAs) are popular devices in the realisation of circuits as it can implement any Boolean function. This article proposes a dynamic complementary metal oxide semiconductor (CMOS) PLA based on NOR architecture that uses a secondary clock and feedback phenomena for low energy and high speed. Static power reduction is achieved by blocking the static current flow during evaluation period. The proposed design is simulated at 45 nm CMOS technology using CADENCE VLSI design tool. With respect to the latest low-energy and fastest PLA reported in the literature, the proposed design is 69% faster and consumes 73% less energy.

Power-area trade-off in power gated FSM synthesis

Partitioning and state encoding of FSM is done to minimise power consumption of final power gated circuit. Partitioning of the FSM into two sub-FSMs and then power gating the inactive sub-FSM incorporates some extra circuitry that increases the total area. So, power consumption is minimised, but at cost of increase in area. To get the power and area optimised power gate implemented circuit, we need to check the variation in power and area by varying weights associated with power and area during partitioning and encoding of FSM targeting power gated synthesis and then fix the weights for power and area for power and area optimised FSM synthesis. In this paper genetic algorithm has been used to find the power-area trade off during partitioning and state encoding of FSM for its power gated implementation. The trade-offs has been determined for different boundary depths.

Thermal aware AND-OR-XOR network synthesis

An essential job of combinational logic synthesis is to optimize the area and power of the synthesized circuit. Two-level and three level logic minimization for area and power are the well researched areas. Recently temperature minimization has been emerged as the new dimension in logic synthesis. Thermal aware AND-OR-XOR network realization is considered in this research work. In this paper attention has also been drawn towards multilevel realization of the corresponding AND-OR-XOR circuit to get a final circuit that is optimized in terms of area as well as power density. Power density is the measure of temperature, so, this work targets the thermal aware multi level synthesis by optimizing power density. The optimization algorithm used here is Genetic algorithm. The final optimized circuit is then simulated in Cadence Encounter and HotSpot tool to get the absolute temperature.

Power Reduction by Integrated Within_Clock_Power Gating and Power Gating (WCPG_in_PG)

Leakage and switching power of circuit can be minimised in FSM based power gating technique by partitioning and encoding of FSM.Depending on the state of machine, at a time one sub-FSM is in power gated mode, but other one is in active mode which continues to dissipate power.In active sub-FSM, it is possible to reduce leakage, if the clock period is larger than the critical path delay of the sub-FSM, then there is a certain portion within the clock period which is idle and in this period power gating may be used.The objective of the paper is to reduce leakage power of active sub-FSM and to reduce leakage and switching power of inactive sub-FSM. So, this paper presents a new architectural technique, called WCPG_in_PG to minimize the overall power.WCPG_in_PG architecture of ISCAS89 benchmark circuit has been implemented and simulated in CADENCE VLSI tool at 45nm technology.