Sameer Wadhwa

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symposium on vlsi technology | 2014

Sam Yang; Lixin Ge; Jeff Lin; Michael Han; Da Yang; Joseph Wang; Kasim Mahmood; Tony Song; Dana Yuan; Dongwon Seo; Marzio Pedrali-Noy; Dinesh Jagannath Alladi; Sameer Wadhwa; Xiaoliang Bai; Liang Dai; Sei Seung Yoon; Esin Terzioglu; Seyfi Bazarjani; Geoffrey Yeap

Despite improved device performance over traditional Poly-SiON technology, high-K metal gate flow introduces additional device variations not previously seen in Poly-SiON process, especially impacting large dimensional (WxL) devices for matching critical applications. For the first time, we report a comprehensive analysis of device variations introduced from metal gate process, GDIM and GGIM, and their sensitivity to circuit layout. Design optimization and verification mechanisms are developed to mitigate metal gate process induced variations in analog matching circuits. After co-optimization, DAC Vt mismatch is reduced by 2.1X and ADC comparator speed is improved by 23.5% in the analog blocks of an advanced mobile SoC currently in production.

Archive | 2011