Marzio Pedrali-Noy

10.1 A 28nm DSP powered by an on-chip LDO for high-performance and energy-efficient mobile applications

A very-long instruction word (VLIW) Hexagon™ DSP is fabricated using a 28 nm high-κ metal-gate process technology optimized for mobile applications [1]. The DSP is designed for a heterogeneous computing environment. It targets high performance and low power across a wide variety of multimedia and modem applications, under aggressive area targets. Its architecture pursues high IPC as opposed to high frequency [2]. It includes a 32 kB L1 data cache (D

High performance mobile SoC design and technology co-optimization to mitigate high-K metal gate process induced variations

), a 16 kB L1 instruction cache (I

Supply-regulated phase-locked loop (pll) and method of using

), and a 256 kB L2 cache.

SUPPLY-REGULATED VCO ARCHITECTURE

Despite improved device performance over traditional Poly-SiON technology, high-K metal gate flow introduces additional device variations not previously seen in Poly-SiON process, especially impacting large dimensional (WxL) devices for matching critical applications. For the first time, we report a comprehensive analysis of device variations introduced from metal gate process, GDIM and GGIM, and their sensitivity to circuit layout. Design optimization and verification mechanisms are developed to mitigate metal gate process induced variations in analog matching circuits. After co-optimization, DAC Vt mismatch is reduced by 2.1X and ADC comparator speed is improved by 23.5% in the analog blocks of an advanced mobile SoC currently in production.