Sami Karvonen

A low noise quadrature subsampling mixer

Noise analysis of a subsampling mixer structure based on current signal sampling is performed. The calculations show that a promisingly low noise figure can be obtained. The results of the analysis are verified by high-level simulations and measurements of a test circuit designed for quadrature downconversion from a 1st IF of 44.87 MHz to a low IF of 13 kHz.

A CMOS quadrature charge-domain sampling circuit with 66-dB SFDR up to 100 MHz

A charge-domain quadrature sampling circuit realization in 0.35 /spl mu/m CMOS is presented. The circuit downconverts a real-valued IF input signal with a nominal frequency of 50 MHz into baseband quadrature components by decimation. Based on multiple integrative sampling of charge, the circuit integrates a 192-tap complex bandpass finite-impulse response filtering function into the sampling operation providing 18 dB of built-in anti-aliasing suppression for the nearest unwanted frequencies aliasing to dc and over 36 dB of image band rejection on the 923-kHz 3-dB bandwidth of the circuit. The measured third-order input intercept point is + 25 dBV at 50 MHz, while the spurious-free dynamic range is more than 66 dB up to 100-MHz IF input frequency. The power consumption excluding output buffers is 30 mW from a 3.3-V supply.

A quadrature charge-domain sampler with embedded FIR and IIR filtering functions

A circuit technique for integrating built-in complex finite-impulse-response (FIR) and infinite-impulse-response (IIR) filtering functions into operation of a subsampler is presented. Based on integrative multiple sampling in the charge domain, the complex FIR filtering function of the sampler provides internal anti-aliasing and image band suppression prior to quadrature downconversion by subsampling. The complex IIR filtering function, taking place at the output sampling rate of the sampler, performs further first-order channel selection filtering on the downconverted signal. An example 50-MHz IF-sampler implementation in 0.8-/spl mu/m BiCMOS demonstrating the feasibility of the technique is presented in the paper.

On the effects of timing jitter in charge sampling

The effects of random independent timing jitter in integrating charge sampling circuits are analyzed in the time domain. An analytical expression for the signal-to-noise ratio (SNR) of a simple charge sampling circuit and an approximate formula for the SNR of a multiple charge sampling circuit due to timing jitter are given. Numerical Matlab simulations validating the presented theory are shown in the paper.

Charge-domain FIR sampler with programmable filtering coefficients

A charge-domain sampling technique for realization of mixed-mode finite-impulse response (FIR) filters is presented. The method is based on weighting signal current samples integrated into a sampling capacitor with a set of parallel digitally controlled current-mode switches each carrying a unit current element. The fine achievable resolution and digital controllability of the filter tap coefficients allows realization of advanced programmable FIR filtering functions embedded into high-frequency signal sampling. Circuit-level simulation results of an example 50-MHz IF-sampler with a built-in 22-tap complex bandpass sinc/sup 3/ FIR function in 0.35-/spl mu/m CMOS are shown, demonstrating the feasibility of the presented method.

Highly linear G/sub m/ element for high-frequency applications

A constant-Gm highly linear transconductance (Gm ) cell based on the use of a linear passive resistor and feedback technique is presented. The high-frequency linearity properties of the circuit are investigated using the Volterra analysis method. Simulation results of a linearity-optimized Gm element in 0.35 mum CMOS are presented showing a THD of -75.7 dB at 50 MHz for a 1.8 Vp-p input signal

A complex charge sampling scheme for complex IF receivers

A charge sampling technique for complex filtering and further quadrature downconversion of an I/Q downconverted IF signal is introduced. The presented technique can be applied to complex IF radio receivers for attenuating the image signal at the IF and for partial channel selection filtering. Circuit level simulations of a test circuit for complex filtering and quadrature downconversion of a 50 MHz I/Q IF signal are shown.

Charge sampling mixer with /spl Delta//spl Sigma/ quantized impulse response

A novel technique for increasing the selectivity of a charge subsampling mixer is introduced. The technique is based on the utilization of a /spl Delta//spl Sigma/ quantized impulse response with the FIR filtering effect resulting from multiple charge sampling. A possible circuit-level realization of the proposed technique and an example filter response are shown in the paper.

A 50-MHz CMOS quadrature charge sampling circuit with 66 dB SFDR

The quadrature charge sampling circuit realization in 0.35/spl mu/m CMOS is presented. The circuit performs complex band-pass filtering for a real-valued 50-MHz IF input signal providing 18 dB of inherent anti-aliasing rejection and downconverters it into baseband quadrature (I/Q) components by subsampling. The measured 3rd-order input intercept-point (IIP/sub 3/) is +25 dBV at 50 MHz, while the spurious-free dynamic range (SFDR) is more than 66 dB up to 100 MHz operating frequency. The power consumption without output buffers is 30 mW from a 3.3 V supply.

A 50-MHz BiCMOS quadrature charge sampler and complex bandpass SC filter for narrowband applications

An implementation of a quadrature charge sampler and a complex bandpass switched-capacitor (SC) filter in 0.8 /spl mu/m BiCMOS applicable to narrowband low-IF receivers is presented. The circuit quadrature downconverts a 49.85-MHz IF input signal to a low IF of 15 kHz by charge-mode subsampling and performs further complex narrowband filtering on the signal. The measured image rejection is more than 44 dB on the 26.3 kHz -3 dB bandwidth.