Tom A. D. Riley

Delta-sigma modulation in fractional-N frequency synthesis

A description is given of a delta-sigma ( Delta - Sigma ) modulation and fractional-N frequency division technique for performing indirect digital frequency synthesis using a phase-locked loop (PLL). The use of Delta - Sigma modulation concepts results in beneficial shaping of the phase noise (jitter) introduced by fractional-N division. The technique has the potential to provide low phase noise, fast settling time, and reduced impact of spurious frequencies when compared with existing fractional-N PLL techniques. >

An agile ISM band frequency synthesizer with built-in GMSK data modulation

In this paper, a high-resolution fractional-N RF frequency synthesizer is presented which is controlled by a fourth-order digital sigma-delta modulator. The high resolution allows the synthesizer to be digitally modulated directly at RF. A simplified digital filter which makes use of sigma-delta quantized tap coefficients is included which provides built-in GMSK pulse shaping for data transmission. Quantization of the tap coefficients to single-bit values not only simplifies the filter architecture, but the fourth-order digital sigma-delta modulator as well. The synthesizer makes extensive use of custom VLSI, with only a simple off-chip loop filter and VCO required. The synthesizer operates from a single 3-V supply, and has low power consumption. Phase noise levels are less than -90 dBc/Hz at frequency offsets within the loop bandwidth. Spurious components are less than -90 dBc/Hz over a 19.6-MHz tuning range.

A simplified continuous phase modulator technique

A low cost GMSK (Gaussian minimum shift keying) modulation technique is presented. GMSK is chosen as an example although the technique is suitable for any continuous phase constant envelope modulation with discriminator, differential or coherent detection in the targeted receiver. In this technique, a fractional-N synthesizer is used to control the instantaneous frequency and phase of the phase locked synthesizer output. As a result of this approach, no in-phase and quadrature mixer or D/A converters are required. Furthermore, the desired signal can be generated directly at RF with no IF conversion stages. The look-up table to generate the modulation is only one bit wide. /spl Delta/-/spl Sigma/ techniques are used to obtain high accuracy through the long term average of a sequence of the single bits. The narrow band filtering of the transmit data is accomplished in two parts, a precise digital linear phase band-reject part using the one bit stored ROM look-up table and a less precise low pass analog part inherent to the PLL of the synthesizer. >

Design and realization of a digital /spl Delta//spl Sigma/ modulator for fractional-n frequency synthesis

The basic operation of a fractional-n frequency synthesizer has been published, but to date little has been presented on the digital /spl Delta//spl Sigma/ modulators which are required to drive such synthesizers. This paper provides a tutorial overview, which relates digital /spl Delta//spl Sigma/ modulation to other applications of /spl Delta//spl Sigma/ modulation where the literature is more complete. The paper then presents a digital /spl Delta//spl Sigma/ modulator architecture which is economical and efficient and which is practical to realize with commercially available components in comparison with other possible implementations which require extensive custom very large-scale integration (VLSI). A demonstration is made of a 28-b modulator using the architecture presented, which provides a 25-MHz tuning bandwidth and <1-Hz frequency resolution. The modulator is demonstrated in an 800-MHz frequency synthesizer having phase noise of -90 dBC/Hz at a 30-kHz offset.

An interpolated frequency-hopping spread-spectrum transceiver

A technique of spread-spectrum transmission, interpolated frequency-hopping (IFH), is presented. IFH employs a carrier that moves smoothly and continuously in frequency, helping to alleviate problems, such as spectral splatter and transient mismatch, which are a concern in conventional phase-locked loop (PLL)-based frequency-hopping spread-spectrum systems. In IFH, the pseudorandom hopping code is passed through a digital interpolation filter prior to controlling the synthesizer instantaneous frequency output. While such filtering is commonly used in data pulse-shaping to improve the spectral characteristics of the modulated carrier, such filtering has not been reported for IFH codes, where the frequency deviations are changing and can span several MHz. The implications of matching the transient responses of two PLL-based frequency synthesizers using this method have also not been reported. Initial simulation and laboratory measurements indicate that, for certain cases, IFH shows a 1.9 dB improvement in received IF power, has a much sharper roll-off of inband phase noise when compared to conventional hopping, and provides a phase-coherent IF after despreading. An IFH transceiver system using /spl Delta/-/spl Sigma/ frequency synthesis and a /spl Delta/-/spl Sigma/ frequency discriminator is proposed. The system would be suitable for integrated mobile radio applications in slow-fading environments.

A single-loop second-order /spl Delta//spl Sigma/ frequency discriminator

A new single-loop architecture for a second-order /spl Delta//spl Sigma/ frequency discriminator suitable for RF applications is presented. This architecture can be realized using mostly digital blocks and has several advantages over multi-loop structures which are susceptible to analog non-idealities. A 2 GHz version of the /spl Delta//spl Sigma/ frequency discriminator targeted to wireless mobile applications has been implemented in a 0.8 /spl mu/m BiCMOS process. Measured results show a peak signal-to-noise ratio of 45 dB in a 200 kHz bandwidth.

A /spl Sigma/-/spl Delta/ frequency discriminator based synthesizer

A new architecture is proposed for a synthesizer suitable for mobile radio applications. This architecture has several advantages over the fractional-N type architectures currently used. The new synthesizer is based on an oversampled /spl Sigma/-/spl Delta/ frequency discriminator in the feedback path which converts the frequency to digital form. This results in a largely digital architecture that eliminates many of the analog noise sources that plague conventional fractional-N synthesizers.

A Second Order ΔΣ Frequency Discriminator with Fractional-N Divider and Multi-Bit Quantizer

The analysis and design of a new ΔΣ frequency discriminator (FD) architecture is presented in this paper. This architecture has finer frequency resolution and lower noise compared to existing architectures. This superior performance is achieved by incorporating a fractional-N divider and a multi-bit quantizer. This new architecture is based on ΔΣ modulation techniques and converts instantaneous frequency directly to digital form. System level simulation models were developed in Matlab Simulink to explore the effects of various parameters on performance. The architecture was then partitioned into circuit blocks. Each of the circuit blocks was simulated at both the behavioural and the transistor level. This FD architecture is suitable for high resolution frequency synthesis.

A 0.009–1.4-GHz Frequency Synthesizer With Suppressed Transients During VCO Band Switching

This brief presents a 0.009-1.4-GHz frequency synthesizer that is able to compensate for changes in the frequency tuning range, due to temperature variations, by switching voltage-controlled oscillator (VCO) bands with minimal phase and frequency errors, without cycle slipping and without introducing any phase offsets. This is accomplished by a subthreshold capacitor bank switching circuit that causes the gradual addition of capacitance slowly enough to allow the loop to adjust the VCO control voltage to compensate. The additional circuitry uses less than 0.001 mm2 of silicon area and has minimal power consumption and minimal effects on the synthesizers phase noise when fully switched. The synthesizer used to demonstrate this was implemented in a 0.18-μm SiGe BiCMOS process and achieves 365-fs integrated jitter at 1.05 GHz, with a total power consumption of 81 mW. Measurements of the capacitor bank switching circuit shows that it prevents cycle slipping during band switching and reduces the maximum frequency deviation by 99.3%.

A fractional ΔΣ phase-to-digital converter for digitizing a phase-locked loop

This paper presents a circuit architecture for digitizing the VCO phase in a digital phase locked loop. The proposed architecture functions as a ΔΣ modulator in the phase domain to achieve noise shaping, and uses a Digital-To-Time Converter to achieve a fractional phase quantization step. The combination of the ΔΣ noise shaping and fractional quantization reduces quantization phase noise both in-band and out-of-band. Proof of concept is achieved using an event-driven VHDL model.