Samiha Mourad

On the Reliability of the IBM MVS/XA Operating System

This paper describes an analysis of system-detected errors on the MVS operating system under the eXtended Architecture (XA) for two IBM 3081 systems. The analysis classifies the errors in categories and examines the effectiveness of the recovery system of the MVS/XA. Comparison of the results for the two IBM 3081s confirm the dependence of the error distribution on the type of system utilization. The results for one of the machines are compared to those obtained for the same system when operating under MVS/SP. The comparison of the MVS/XA to the MVS/SP reveals the following: more addressing errors, a better error recording system and improved reliability and fault tolerance.

Digital Logic Implementation in Memristor-Based Crossbars - A Tutorial

A memristor is a passive electronic device that was proposed and described by Leon Chua in 1971. The first practical implementation has been realized by Stan Williams’ group at HP Labs in 2008. The goal of this paper is to give the reader a brief introduction to the possibilities of logic design using memristors. It paper is intended as a tutorial on how to use memristor crossbars for logic design and is a consolidation of various recent publications.

Performance of submicron CMOS devices and gates with substrate biasing

This paper reports the results of an extensive simulation to study the effect of body bias engineering on the performance of deep submicron technology circuits. Reverse body bias (RBB) is very useful in reducing a devices off-state leakage current and hence standby power. This reduction is more effective as the temperature increases. Forward body bias (FBB) suppresses short channel effects and hence improves V/sub t/ roll-off and reduces the gate delays. This improvement is enhanced as the power supply voltage decreases. However, the power dissipation and power delay product have increased under this biasing condition. A good strategy is to apply a forward body bias on critical path only to improve speed without significant increase in power dissipation.

Multiple stuck-at fault testability of self-testing checkers

As a feasibility study on offline testing of VLSI systems with concurrent error checking capability, the multiple fault testability is evaluated for self-testing checkers. New offline testing schema called codeword testing and noncodeword testing are introduced, in which all codewords and a small number of noncodewords are used as test inputs and the checker outputs are observed to decide if the circuit under test is faulty or not. It is proved that all the multiple stuck-at faults in tree-structured two-rail code checkers are detected with codeword testing followed by noncodeword testing. It is shown by simulation experiments that codeword testing can detect more than 99% of all possible double and triple faults in existing self-testing checkers for two-rail codes, Berger codes, and k-out-of-2k codes. The simulation experiments also show that all of the double and triple faults that elude the codeword testing are detected by noncodeword testing in which a small number of noncodewords are needed.<<ETX>>

Controllable LFSR for BIST

This paper presents the preliminary results for a novel mixed-mode scheme to generate test patterns for random pattern resistant faults. It is based on a programmable method in contrast to the hardware implementation used so far. It not only guarantees the full test coverage in the combinational stuck-at faults, but also can be extended to the sequential or delay path testing. The result shows that the full test coverage was possible with the smaller size of control vectors, up to a 70% reduction in size from the original scan test vectors.

Self-reset logic for fast arithmetic applications

A new family of self-reset logic (SRL) cells is presented in this paper. The single-ended basic structure proposed realizes an incomplete logic family, since it is incapable of inverting logic. Thus, a dual-rail SRL (DRSRL) implementation is also proposed. These cells maintain small delay variations for all input combinations, once minimum timing requirements on inputs are satisfied, and produce output pulses of fairly constant width for varying fanout, leaving enough headroom in the design to accommodate process, supply voltage, and temperature variations. These properties simplify the implementation of data-path and control circuits where the logic depth does not affect the stage output pulse width, eliminating the need for pulse-width controlling circuits required in previous works on SRL. In SRL, power is consumed only if new data are pumped through the logic. The clock grid is limited to the registers that launch and receive the signal path. The clocking overhead is thus reduced, compared with other dynamic designs, and it is especially suitable for wave pipelining. Case study examples and simulated characterization data are included to show the design methodology.

Modeling the effect of ground bounce on noise margin

In integrated circuits, ground bounce is the voltage developed across the inductance of the power supply leads as a result of the current surge through switching gates. It causes distortion of circuit output waveforms that can interfere with testing. This paper describes a simple circuit model that can be used to estimate the ground bounce waveform that appears on both switching and nonswitching outputs of CMOS circuits as a result of ground bounce. The model includes the effects of several circuit parameters on the waveform and has been validated by extensive Spice simulation.

A new model for metastability

Metastability has been long documented as a problem in digital systems with asynchronous inputs. This problem has been analyzed in CMOS latches using a 2nd order small signal model. However, uses of a third order model taking into account that the effect of the feedback transistors is necessary for correct modeling of metastability. A new simulator was developed for this study. The results presented here show that when modeling a CMOS latch for metastability purposes, it is not sufficient to use a second order circuit that neglects the effect of the feedback transistor. The simulator can also be used to study the effect of power supply noise and applied to interconnect models to study crosstalk.

Embedded test control schemes for compression in SOCs

This paper presents novel control schemes for testing embedded cores in a system on a chip (SOC). It converts a traditional BIST scheme into an externally controllable scheme to achieve a high test quality within optimal test execution time without inserting test points. The scheme promotes design and test reuse without revealing IP information.

Crosstalk Induced Fault Analysis and Test in DRAMs

This study analyzes the effects of crosstalk-induced faults due to parameter variation during the manufacture of DRAMs. The focus is on read operations, which are sensitive to crosstalk and to neighborhood data patterns. Analytical studies and numerical simulations have been used to investigate a class of crosstalk reading faults (CRF) that read operations are susceptible to. The results reveal that there exist worst case data patterns in each physical RAM block and cell arrangement. The worst case data pattern occurs when neighboring and victim bit-lines switch to opposite values at the same time. If the bit-line arrangement is known, the test for the CRFs is quite trivial. If there is no knowledge of the internal chip structure, a deterministic pattern cannot be assigned and therefore a generic test method is needed. In this paper, a test algorithm is proposed that exhausts every state of any 3 or 5 bit-lines of a RAM block.