Pak K. Chan

Spectral K-way ratio-cut partitioning and clustering

Recent research on partitioning has focused on the ratio-cut cost metric, which maintains a balance between the cost of the edges cut and the sizes of the partitions without fixing the size of the partitions a priori. Iterative approaches and spectral approaches to two-way ratio-cut partitioning have yielded higher quality partitioning results. In this paper, we develop a spectral approach to multi-way ratio-cut partitioning that provides a generalization of the ratio-cut cost metric to L-way partitioning and a lower bound on this cost metric. Our approach involves finding the k smallest eigenvalue/eigenvector pairs of the Laplacian of the graph. The eigenvectors provide an embedding of the graphs n vertices into a k-dimensional subspace. We devise a time and space efficient clustering heuristic to coerce the points in the embedding into k partitions. Advancement over the current work is evidenced by the results of experiments on the standard benchmarks. >

Spectral K-Way Ratio-Cut Partitioning and Clustering

Recent research on partitioning has focussed on the ratio-cut cost metric which maintains a balance between the sizes of the edges cut and the sizes of the partitions without fixing the size of the partitions a priori. Iterative approaches and spectral approaches to two-way ratio-cut partitioning have yielded higher quality partitioning results. In this paper we develop a spectral approach to multiway ratio-cut partitioning which provides a generalization of the ratio-cut cost metric to k-way partitioning and a lower bound on this cost metric. Our approach involves finding the k smallest eigenvalue/eigenvector pairs of the Laplacian of the graph. The eigenvectors provide an embedding of the graphs n vertices into a k-dimensional subspace. We devise a time and space efficient clustering heuristic to coerce the points in the embedding into k partitions. Advancement over the current work is evidenced by the results of experiments on the standard benchmarks.

Routability-driven technology mapping for lookup table-based FPGA's

A new algorithm for technology mapping of lookup table-based Field-Programmable Gate Arrays (FPGAs) is presented. It has the capability of producing compact designs (minimizing the number of cells (CLBs)), as well as the flexibility of trading routability with compactness of a design. Research in this area has focussed on minimizing the number of cells. However, minimizing the number of cells without regard to routability is ineffective. Since placement and routing is really the most time-consuming part of the FPGA design process, producing a routable design with a slightly larger number of cells is preferable than producing a design using fewer cells which is difficult to route, or in the worst case unroutable. We have implemented our algorithm in the Rmap program, and studied routability of two other mappers with respect to Rmap. Rmap produces mappings with better routability characteristics, and more significantly Rmap produces routable mappings when other mappers do not. >

Architectural tradeoffs in field-programmable-device-based computing systems

Reprogrammable Field-Programmable Gate Arrays (FPGAs) have enabled the realization of high-performance and affordable reconfigurable computing engines. The authors examine the architectural tradeoffs involved in designing general purpose FPGA-based computing systems with field-programmable gate arrays and field-programmable interconnects. The fact that FPGAs provide both programmable logic and programmable interconnects raises numerous design issues that need to be considered with care. Factors that influence the tradeoffs are routability, rearrangeability and speed.<<ETX>>

Algorithms for library-specific sizing of combinational logic

We examine the problem of choosing the proper sizes from a cell library for the logic elements of a Boolean network to meet timing constraints on the propagation delay along every path from the primary input to the primary output. If the Boolean network has a tree topology, we show that there exists a pseudo-polynomial time algorithm for finding the optimal solution to this problem. A backtracking-based algorithm for finding feasible solutions for networks that are not trees is also suggested and evaluated.

On Routability Prediction for Field-Programmable Gate Arrays

Efficient utilization of Field Programmable Gate Arrays (FPGAs) depends on the ability to determine whether designs will exceed the logic or routing capacities of the devices. Here, we focus on the problem of assessing the routability of designs for FPGAs before place-and-route. Specifically, we identify the relevant wireability theories, modify and adapt the theories for FPGAs, and conduct experiments to validate the theories.

Multi-level spectral hypergraph partitioning with arbitrary vertex sizes

This paper presents a new spectral partitioning formation which directly incorporates vertex size information. The new formulation results in a generalized eigenvalue problem, and this problem is reduced to the standard eigenvalue problem. Experimental results show that incorporating vertex sizes into the eigenvalue calculation produces results that are 50% better than the standard formation in terms of scaled ratio-cut cost, even when a Kernighan-Lin style iterative improvement algorithm taking into account vertex sizes is applied as a post-processing step. To evaluate the new method for use in multi-level partitioning, we combine the partitioner with a multi-level bottom-up clustering algorithm and an iterative improvement algorithm for partition refinement. Experimental results show that our new spectral algorithm is more effective than the standard spectral formulation and other partitioners in the multi-level partitioning of hypergraphs.

Computing signal delay in general RC networks by tree/link partitioning

Most RC simulators handle only tree networks, not arbitrary networks. An algorithm is presented for computing signal delays in general RC networks using the RC-tree computation as the primary operation. The algorithm partitions a given network into a spanning tree and links. It computes the signal delay of the spanning tree, and updates the signal delay as it incrementally adds the links back to reconstruct the original network. If m is the number of links, this algorithm requires m(m+1)/2 updates and m+1 tree delay evaluations. All the tree delay evaluations involve computing signal delays with the same resistive spanning tree, but with different values for the capacitors. >

Delay optimization of carry-skip adders and block carry-lookahead adders using multidimensional dynamic programming

The worst-case carry propagation delays in carry-skip adders and block carry-lookahead adders depend on how the full adders are grouped structurally together into blocks as well as the number of levels. The authors report on a multidimensional dynamic programming paradigm for configuring these two adders to attain minimum latency. Previous methods are applicable only to very limited delay models that do not guarantee a minimum latency configuration. Under the delay model, critical path delay is calculated not only taking into account the intrinsic gate delays, but also the fanin and fanout contributions. >

Routability-driven technology mapping for lookup table-based FPGAs

An algorithm for technology mapping of lookup-table-based field-programmable gate arrays is presented. It has the capability of producing slightly more compact designs than some existing mappers, and it offers the flexibility of trading routability with compactness of a design. The algorithm is implemented in the Rmap program and routability is compared with that of two other mappers. It is found that Rmap can produce mappings with better routability characteristics, and it produces routable mappings when other mappers do not.<<ETX>>