Sandeep K. Arya

LEVEL SHIFTER DESIGN FOR LOW POWER APPLICATIONS

With scaling of Vt sub-threshold leakage power is increasing and expected to become significant part of total power consumption In present work three new configurations of level shifters for low power application in 0.35{\mu}m technology have been presented. The proposed circuits utilize the merits of stacking technique with smaller leakage current and reduction in leakage power. Conventional level shifter has been improved by addition of three NMOS transistors, which shows total power consumption of 402.2264pW as compared to 0.49833nW with existing circuit. Single supply level shifter has been modified with addition of two NMOS transistors that gives total power consumption of 108.641pW as compared to 31.06nW. Another circuit, contention mitigated level shifter (CMLS) with three additional transistors shows total power consumption of 396.75pW as compared to 0.4937354nW. Three proposed circuits shows better performance in terms of power consumption with a little conciliation in delay. Output level of 3.3V has been obtained with input pulse of 1.6V for all proposed circuits.

Large signal analysis of FM-AM conversion in dispersive optical fibers for PCM systems including second order dispersion

By using large signal analysis for dispersive optical fiber, the FM-AM conversion with respect to binary intensity modulated PCM systems including second order dispersion term is discussed. The modified expression for power penalty has been derived and its impact on laser linewidth and bit rate has been investigated. For power penalty less than 0.5 dB, the plots between bit rate and transmission distance are plotted. It is seen that the transmission distance increases with decrease in linewidth over significant bit rates. The transmission distance with first order dispersion term for 300 MHz linewidth is approximately 800km. With proper first order dispersion compensation, i.e., with second order dispersion only, the transmission distance can be enhanced to 10 8 km for this linewidth. The linewidth requirements for systems with different bit rates and transmission distances are also calculated and discussed. Further, it is seen that by including the second-order dispersion term, the bit rate and transmission distance decreases. For higher linewidths, this decrease in bit rate and transmission distance is very less and vice versa. For 300 MHz linewidth, the decrease in transmission distance is just 30 km, and for 30 MHz linewidth, the decrease is approximately 600 km over significant bit rates.

CMOS Development and Optimization, Scaling Issue and Replacement with High-k Material for Future Microelectronics

development and optimization of Silicon technology has been guided by CM OS scaling theory (1) and predications made by Semiconductor Industry (SIA) in the International Technology Roadmap for Semiconductor (ITRS). With the trend of scaling down of Complementary M etal Oxide Semiconductor (CMOS) transistor as Moores Law (2) requires replacement of conventional silicon dioxide layer with the higher permittivity material for gate dielectric. As the silicon industry moves to 32nm technology node and beyond complaints like leakage and power dissipation dominates. M anaging such issues are crucial factors for reliable high speed operation and chip design. Although scaling will continue for couple of decades but device geometries reaches to atomic size and limitation of quantum mechanical physical boundaries. To address these problems there is need of innovation in material science & engineering, device structure, and new nano devices based on different principle of physics. Here we have elaborated about scaling issues and alternate high-k dielectric for M etal Oxide Semiconductor Field Effect Transistor (M OSFET). Introducing a high-k material may replace todays silicon dioxide technology and can also provide extendibility over several generations. C-V analyses have been studied for various M OS capacitor with conventional SiO2 and also with high-k material like Gd 2O 3, ZrO2, HfO2, and TiO2.

Comparison of Time-Delay Estimation Techniques in Acoustic Environment

The calculation of time delay between a signal and its echo received at a microphone has been proven to be a useful parameter. Speech enhancement, speaker localization, speech and speaker recognition are few applications of TDE methods. We are implementing various methods for the estimation of time delay. These methods are implemented in MATLAB. The reason for choosing the MATLAB as the analysis and simulation tool is that it has more flexible choices to support the simulation and is easy to do modification or data recording. These methods are crosscorrelation (CC), phase transform (PHAT). Various time-delay estimation techniques based on the cross-correlation functions are compared through simulations and measurements. Their simulation results are compared in terms of computation complexity, hardware implementation, precision, and accuracy.

Design of CMOS Energy Efficient Single Bit Full Adders

Here, three new low power single bit full adders using 9 and 10 transistor have been presented. The proposed adders have the advantage of low power consumption with small area requirements due less number of transistors. Low power objective has been achieved at circuit level by designing the adder with optimized XOR gates and multiplexer approach. Direct path between supply voltage and ground have been minimized in these designs. The circuits have been simulated in 0.18μm CMOS technology using SPICE. The first adder shows power dissipation of 23.8595pW with maximum output delay of 67.5566fs at supply voltage of 1.8V. The second adder shows power dissipation of 43.1258pW with maximum output delay of 58.9935fs. Third adder shows power dissipation of 33.5163pW with delay of 62.065fs. Further, simulations have been carried out with different supply voltage [1.8 - 3.3] V. Power consumption of proposed full adders have been compared with earlier reported circuits and proposed circuit’s shows better results.

Digitally controlled oscillator design with a variable capacitance XOR gate

Digitally Controlled Oscillator (DCO) designs using three transistors XNOR gates as variable capacitance load are presented in this study. Two different design approaches for five- and seven-stage DCOs were reported. Output frequencies were controlled digitally with digital bits applied to delay cells. Five-bit controlled DCO using delay cell-I showed frequency and power variation of 1.5335-2.0526 GHz and 2.5906-2.4271 mW, respectively, by varying control word 00000-11111. Moreover, seven-bit controlled DCO showed frequency and power consumption variation of 1.0890-1.4764 GHz and 3.6268-3.3979 mW, respectively, with varying control word 0000000-1111111. Further, five-bit controlled DCO with delay cell-II showed frequency and power variation of 0.77891-1.3840 GHz and 6.5225-6.0320 mW, respectively, with control word variations 00000-11111. Seven-bit DCO showed frequency of 0.58322-1.0431GHz and power consumption of 9.006-8.3199 mW with control word variation 0000000-1111111. Power consumption, output frequency and Figure of Merit (FoM) of proposed circuits were compared with earlier reported circuits and the present approaches showed significant improvements.

AN OPTIMAL DESIGN OF IIR DIGITAL FILTER USING PARTICLE SWARM OPTIMIZATION

In this article, a novel approach for infinite-impulse response (IIR) digital filters using particle swarm optimization (PSO) is presented. IIR filter is essentially a digital filter with recursive responses. Because the error surface of digital IIR filters is generally nonlinear and multimodal, so global optimization techniques are required in order to avoid local minima. This study is based on a heuristic way to design IIR filters. PSO is a powerful global optimization algorithm introduced in combinatorial optimization problems. This study finds the optimum coefficients of the IIR digital filter through PSO. It is found that the calculated values are more optimal than the FDA tool and GA available for the design of the filter in MATLAB. Design of low-pass and high-pass IIR digital filters is proposed in order to provide an estimate of the transition band. The simulation results of the employed examples show an improvement on the transition band. The stability of designed filters is described by the position of Pole-Zeros.

An Optimal Design of FIR Digital Filter Using Genetic Algorithm

The Paper presents a simple computer-aided design approach for designing Finite Impulse Response (FIR) digital filters. FIR filter is essentially a digital filter with non Recursive responses. Since the error surface of digital FIR filters is generally nonlinear and multimodal, global optimization techniques are required in order to avoid local minima. There are many ways for the design of FIR Digital filters. This Paper Presents soft computing technique for the design of FIR filters. In this Paper, Genetic Algorithm (GA) base evolutionary method is proposed for design of FIR digital filter. GA is a well-known powerful global optimization algorithm introduced in combinatorial optimizations problems. The Simulation result for the employed example is presented in this paper and can be efficiently used for FIR digital filter design.

Dynamic characteristics of vibratory Gyro-accelerometer

Thispaper presents a systematic approach inreaching governing equation for microgyroaccelerometer. The study is focused on to analyze the dynamic characteristics of vibratory microgyroaccelerometer. In this device, the mechanical structure is excited into oscillatory motion. The angular velocity input to the sensor is then multiplied by the periodic driven motion. A demodulation is required to recover the angular velocity input and linear acceleration from the sense responses, as the governing differential equations for the Gyro-accelerometer input and output are time variant. The frequency responses for the time variant linear system is obtained through the demodulation and low pass filtered steady-state output to sinusoidal excitation. The frequency response, thus, obtained are validated with MATLAB Simulink data.

An application of swarm intelligence for the design of IIR digital filters

This paper presents the swarm intelligence (SI)-based particle swarm optimisation (PSO) in context of designing infinite-impulse response (IIR) digital filters. IIR filters are the part of digital filters with recursive responses. Since the error surface of IIR digital filters is generally non-linear and multimodal, global optimisation techniques are required in order to avoid local minima. The particle swarm optimisation algorithm is then applied for calculating optimal coefficients of IIR digital filters and comparison is done preferably with filter design tool and other heuristic techniques. The simulation results of benchmark filter are discussed in this paper and can be efficiently used for IIR digital filter design.