Sujata Pandey

LEVEL SHIFTER DESIGN FOR LOW POWER APPLICATIONS

With scaling of Vt sub-threshold leakage power is increasing and expected to become significant part of total power consumption In present work three new configurations of level shifters for low power application in 0.35{\mu}m technology have been presented. The proposed circuits utilize the merits of stacking technique with smaller leakage current and reduction in leakage power. Conventional level shifter has been improved by addition of three NMOS transistors, which shows total power consumption of 402.2264pW as compared to 0.49833nW with existing circuit. Single supply level shifter has been modified with addition of two NMOS transistors that gives total power consumption of 108.641pW as compared to 31.06nW. Another circuit, contention mitigated level shifter (CMLS) with three additional transistors shows total power consumption of 396.75pW as compared to 0.4937354nW. Three proposed circuits shows better performance in terms of power consumption with a little conciliation in delay. Output level of 3.3V has been obtained with input pulse of 1.6V for all proposed circuits.

Design of CMOS Energy Efficient Single Bit Full Adders

Here, three new low power single bit full adders using 9 and 10 transistor have been presented. The proposed adders have the advantage of low power consumption with small area requirements due less number of transistors. Low power objective has been achieved at circuit level by designing the adder with optimized XOR gates and multiplexer approach. Direct path between supply voltage and ground have been minimized in these designs. The circuits have been simulated in 0.18μm CMOS technology using SPICE. The first adder shows power dissipation of 23.8595pW with maximum output delay of 67.5566fs at supply voltage of 1.8V. The second adder shows power dissipation of 43.1258pW with maximum output delay of 58.9935fs. Third adder shows power dissipation of 33.5163pW with delay of 62.065fs. Further, simulations have been carried out with different supply voltage [1.8 - 3.3] V. Power consumption of proposed full adders have been compared with earlier reported circuits and proposed circuit’s shows better results.

Digitally controlled oscillator design with a variable capacitance XOR gate

Digitally Controlled Oscillator (DCO) designs using three transistors XNOR gates as variable capacitance load are presented in this study. Two different design approaches for five- and seven-stage DCOs were reported. Output frequencies were controlled digitally with digital bits applied to delay cells. Five-bit controlled DCO using delay cell-I showed frequency and power variation of 1.5335-2.0526 GHz and 2.5906-2.4271 mW, respectively, by varying control word 00000-11111. Moreover, seven-bit controlled DCO showed frequency and power consumption variation of 1.0890-1.4764 GHz and 3.6268-3.3979 mW, respectively, with varying control word 0000000-1111111. Further, five-bit controlled DCO with delay cell-II showed frequency and power variation of 0.77891-1.3840 GHz and 6.5225-6.0320 mW, respectively, with control word variations 00000-11111. Seven-bit DCO showed frequency of 0.58322-1.0431GHz and power consumption of 9.006-8.3199 mW with control word variation 0000000-1111111. Power consumption, output frequency and Figure of Merit (FoM) of proposed circuits were compared with earlier reported circuits and the present approaches showed significant improvements.

Analytical modeling of drain current and RF performance for double-gate fully depleted nanoscale SOI MOSFETs

A new 2D analytical drain current model is presented for symmetric double-gate fully depleted nanoscale SOI MOSFETs. Investigation of device parameters like transconductance for double-gate fully depleted nanoscale SOI MOSFETs is also carried out. Finally this work is concluded by modeling the cut-off frequency, which is one of the main figures of merit for analog/RF performance for double-gate fully depleted nanoscale SOI MOSFETs. The results of the modeling are compared with those obtained by a 2D ATLAS device simulator to verify the accuracy of the proposed model.

Low power digitally controlled oscillator designs with a novel 3-transistor XNOR gate

Digital controlled oscillators (DCOs) are the core of all digital phase locked loop (ADPLL) circuits. Here, DCO structures with reduced hardware and power consumption having full digital control have been proposed. Three different DCO architectures have been proposed based on ring based topology. Three, four and five bit controlled DCO with NMOS, PMOS and NMOS & PMOS transistor switching networks are presented. A three-transistor XNOR gate has been used as the inverter which is used as the delay cell. Delay has been controlled digitally with a switch network of NMOS and PMOS transistors. The three bit DCO with one NMOS network shows frequency variations of 1.6141–1.8790 GHz with power consumption variations 251.9224–276.8591 μW. The four bit DCO with one NMOS network shows frequency variation of 1.6229–1.8868 GHz with varying power consumption of 251.9225–278.0740 μW. A six bit DCO with one NMOS switching network gave an output frequency of 1.7237–1.8962 GHz with power consumption of 251.928–278.998 μW. Output frequency and power consumption results for 4 & 6 bit DCO circuits with one PMOS and NMOS & PMOS switching network have also been presented. The phase noise parameter with an offset frequency of 1 MHz has also been reported for the proposed circuits. Comparisons with earlier reported circuits have been made and the present approach shows advantages over previous circuits.

A New Low Power Single Bit Full Adder Design with 14 Transistors using Novel 3 Transistors XOR Gate

In present work a new XOR gate using three transistors has been proposed. Design shows adequate output logic levels with noise margin of 2V with 3.3V input signals. XNOR logic, obtained with addition of inverter shows improved noise margin of 3.2V. A new design for single bit full adder has been implemented using proposed XOR/XNOR gates and transmission gate multiplexer. Full adder designed with 14 transistors shows power dissipation of 655.6149μW and maximum output delay 0.11055ns. Proposed adder circuit shows adequate noise margin of 3.2 V for Sum (Sum output) and 2.2V for Cout (Carry output) with supply voltage of 3.3V. Circuit works well with reduced supply voltage and simulations have been carried out up to 1.8V supply voltage. Simulations are performed by using SPICE based on TSMC 0.35μm CMOS technology. Power consumption of proposed full adders has been compared with earlier reported circuits and proposed circuit’s shows better performance in terms of power consumptions and transistor count.

RTL implementation for AMBA ASB APB protocol at system on chip level

In todays era AMBA (advanced microcontroller bus architecture) specifications have gone far beyond the Microcontrollers. In this paper, AMBA (Advanced Microcontroller Bus Architecture) ASB APB (Advanced system bus - Advanced Peripheral Bus) is implemented. The goal of the proposed paper is to synthesis, simulate complex interface between AMBA ASB and APB. The methodology adopted for the proposed paper is Verilog language with finite state machine models designed in ModelSim Version 10.3 and Xilinx-ISE design suite, version 13.4 is used to extract synthesis, design utilization summary and power reports. For the implementation APB Bridge, arbiter and decoder are designed. In AMBA ASB APB module, master gets into contact with APB bus. Arbiter determines masters status and priority and then, starts communicating with the bus. For selecting a bus slave, decoder uses the accurate address lines and an acknowledgement is given back to the bus master by the slave. An RTL view and an extracted design summary of AMBA ASB APB module at system on chip are shown in result section of the paper. Higher design complexities of SoCs architectures introduce the power consumption into picture. The various power components contribute in the power consumptions which are extracted by the power reports. So, power reports generate a better understanding of the power utilization to the designers. These are clocks total power which consumes of 0.66 mW, hierarchy total power which consumes of 1.05 mW, hierarchy total logical power which consumes of 0.30 mW and hierarchy total signal power which consumes of 0.74 mW powers in the proposed design. Graph is also plotted for clear understanding of the breakdown of powers.

Low power approach for implementation of 8B/10B encoder and 10B/8B decoder used for high speed communication

In this paper a clock gated 8B/10B encoder and 10B/8B decoder circuit is implemented. In this we design the encoder decoder circuit with gated clock as it optimized the power without degrading the performance of the circuits. The technology used in this paper is gated clock circuit using negative latch. This gated clock then used to control the encoder and decoder circuit. The RTL view of encoder and decoder with clock gating are shown in Figures 13 and 14. Encoder without clock gating circuit at 20 MHz consumes hierarchy power and on-chip power is 0.10 mW and 111 mW respectively and at 200 MHz consumes hierarchy power and on-chip power is 1.05 mW and 149 mW respectively. Encoder with clock gating circuit at 20 MHz consumes hierarchy power and on-chip power is 0.05 mW and 108 mW respectively and at 200 MHz consumes hierarchy power and on-chip power is 0.47 mW and 113 mW respectively. Decoder without clock gating circuit at 20 MHz consumes hierarchy power and on-chip power is 0.05 mW and 108 mW respectively and at 200 MHz consumes hierarchy power and on-chip power is 0.49 mW and 116 mW respectively. Decoder with clock gating circuit at 20 MHz consumes hierarchy power and on-chip power is 0.05 mW and 108 mW respectively and at 200 MHz consumes hierarchy power and on-chip power is 0.49 mW and 113 mW respectively. The encoder and decoder circuits are design using verilog HDL and are simulated in ModelSim 10.3c. For the RTL view and power report of the implemented circuit we used Xilinx ISE suite 13.4.

A new high speed three stage class B output buffer for LCD applications

In this paper we have proposed a novel buffer amplifier to be used in LCD circuitry. The circuit is implemented on 0.18μm CMOS technology. The new high speed buffer shows the reduction in the value of settling time and also the power dissipation. The settling time of the output buffer for 1000 pF load is 0.94μs. The power consumption for this circuit is 50.89 μWatts. The gain of the new high speed three stage class B output buffer is improved and is 72dB and phase margin is equal to 54.166 degrees. The results obtained are well comparable with the available results.

A Novel Low-Power Design Approach to Exploit the Power Usage of AMBA APB Bridge

In this paper, AMBA advanced peripheral bus bridge (APB Bridge) is implemented with a new design approach. The approach consists of a gated clock and reset controller circuits with APB Bridge for efficient optimization of power and for synchronizing the sequential circuits. Though clock net does not have any significant role in digital computation, it only provides synchronization to the sequential circuits, but unnecessary switching activities of clocks may cause a huge amount of power dissipation around 15–50 %. A proposed approach is to implement the effective gated clock circuit with negative latch to produce a gated clock as an output. This gated clock provides a selective control over clock net that means when a target’s device clock functioning is required at that time controlling device’s clock had been switched off. When the proposed approach is implemented in Verilog as APB Bridge with reset controller, clock power has been reduced to some level and provides power utilization in circuit. Simulation results are verified in ModelSim version 10.3c and then power report is extracted from Xilinx ISE suite 13.4 version. Result of the proposed approach: Total clock domain power of 0.39 mW, total hierarchy power of 0.49 mW, and total on chip power of 0.109 W are consumed by the proposed design. Hence total clock domain power consumption is 27.78 %, total hierarchy power consumption is 47.31 %, and total on chip power consumption is 6.84 % less than the bridge without clock gating and reset controller conditions. Simulation results and power summary reports are also included with the proposed design.