Sandeep Saini

An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects

In VLSI interconnect buffers are used to restore the signal level affected by the parasitics. However buffers have a certain switching time that contributes to overall signal delay. Further the transitions that occur in interconnects also contribute to crosstalk delay. Thus the overall delay in interconnects is due to combined effect of both buffer and crosstalk delay. In this work a replacement of buffers with Schmitt trigger is proposed for the same purpose of signal restoration. Due to lower threshold voltage of Schmitt trigger signal can rise early and the large noise margin of schmitt trigger helps in reducing the noise glitches as well. Simulation results shows that the Schmitt trigger approach gives 20% delay reduction as compared to 10.4% in case of buffers.

A novel design of compact reversible SG gate and its applications

Reversible logic has received great importance in the recent years because of its in-cogitative feature of reduction in power dissipation which is the key requirement in low power digital designs. It has wide applications in advanced computing, low power CMOS design, optical information processing, DNA computing, bio information, quantum computing and nanotechnology. In this paper a new reversible gate is proposed called SG gate. The encoding and decoding logic has been explained with the help of an algorithm and example. This paper proposes a full adder, N bit adder and a N*N bit reversible multiplier using SG gate. The partial products can be generated with the help of a AND gate. A 4 bit architecture of the proposed reversible adder and multiplier is also designed. Thus, this paper provides the initial threshold to building of more complex system which can execute more complicated operations using reversible logic.

A new bus coding technique to minimize crosstalk in VLSI bus

In DSM technology, minimizing the propagation delay and power consumption on buses is the most important design objective in system-on-chip design. In particular, the coupling effects between wires on the bus that can cause serious problems such as crosstalk delay, noise and power consumption. This paper proposes a technique which reduces power consumption data buses which are fed to a DSP/Communication device. The proposed coding technique reduces the transition activity in the input signals and will consequently result in the reduction of power consumption. A new bus coding technique has been proposed to achieve less power reduction in transmission. SPICE simulations are carried out for interconnect lines of different dimensions at various technology nodes (180, 130, 90 and 65 nm). The proposed model reduces the power consumption by upto 35%.

Low Power Interconnect Design

This book provides practical solutions for delay and power reduction for on-chip interconnects and buses. It provides an in depth description of the problem of signal delay and extra power consumption, possible solutions for delay and glitch removal, while considering the power reduction of the total system. Coverage focuses on use of the Schmitt Trigger as an alternative approach to buffer insertion for delay and power reduction in VLSI interconnects. In the last section of the book, various bus coding techniques are discussed to minimize delay and power in address and data buses. · Provides practical solutions for delay and power reduction for on-chip interconnects and buses; · Focuses on Deep Sub micron technology devices and interconnects; · Offers in depth analysis of delay, including details regarding crosstalk and parasitics; · Describes use of the Schmitt Trigger as a versatile alternative approach to buffer insertion for delay and power reduction in VLSI interconnects; · Provides detailed simulation results to support the theoretical discussions. · Provides details of delay and power efficient bus coding techniques

Implementation of low power FFT structure using a method based on conditionally coded blocks

This paper proposes a coding technique which reduces switching activity hence power consumption in FFT structures. This technique involves a sequential creation of conditionally coded blocks in the inputs of FFT structure. These blocks are then converted to low switching activity blocks using the proposed technique and are concatenated to each other in a sequential order to produce the optimized output. To increase the efficiency, the scheme is applied recursively after each concatenation. The performance of proposed method has been tested and it was found that with respect to 2s complement, the average switching activity is reduced by 38% for different bus lengths. The significant reduction in switching activity leads to power savings of 35% for a 16-bit bus. The hardware, used for encoding and decoding purposes, has been designed using Magma© tools.

Design of low power and high speed multiplexer based Thermometer to Gray encoder

This paper presents an improved multiplexer based encoder for flash analog-to-digital converters. The proposed encoder is designed using 2 : 1 multiplexers. This encoder can be configured to operate on thermometer-code with reduced resolution without any extra overhead. This encoder shows the re-configurable property i.e. higher resolution encoder can be configured as lower resolution encoder. This self re-configurable property can be used in adaptive resolution flash ADCs. Gray codes are mainly used in glitch free fast circuit design and in communication for error correction in digital modulation techniques. Simulation results indicate that power, delay and figure of merit of this encoder is less than the existing digital encoders. The encoder is designed in CMOS BSIM4 90nm technology and 1.2V power supply. The power consumption is 69μW with 7.375ns delay and 511.58fJ figure of merit using 1.2V power supply for 5 bit flash ADC.

A Survey of Machine Translation Techniques and Systems for Indian Languages

Machine Translation pertains to translation of one natural language to other by using automated computing. The main objective is to fill the language gap between two different languages speaking people, communities or countries. In India, we have multiple and hugely diverse languages and scripts, hence scope and need of language translation is immense. In this paper, we focus on the current scenario of research in machine translation in India. We have reviewed various important Machine Translation Systems (MTS) and presented preliminary comparison of the core methodology as used by them.

Relative clause based text simplification for improved English to Hindi translation

Language translation is one of the most research and development oriented topic in todays world because of its increasing demand and application. Knowledge of grammar structure of source and target languages is must for translating one language to other. Clauses are an integral part of any language and helps in constructing complex sentences in different contexts. This complication leads to a low score of translation in almost every machine translation engine existing in the world. In this work, we are focusing on relative clause identification and extraction for text simplification. The generated simple sentences are then fed to the existing translation engines for translation. Link Parser based parsing techniques are used to parse the sentence tree. In this work we have focused on achieving better quality of English-Hindi translations. The proposed approach is tested manually on a sufficiently large dataset and shows promising and better translation score than the conventional approaches.

Securing qr codes by rsa on fpga

QR codes, intended for maximum accessibility are widely in use these days and can be scanned readily by mobile phones. Their ease of accessibility makes them vulnerable to attacks and tampering. Certain scenarios require a QR code to be accessed by a group of users only. This is done by making the QR code cryptographically secure with the help of a password (key) for encryption and decryption. Symmetric key algorithms like AES requires the sender and the receiver to have a shared secret key. However, the whole motive of security fails if the shared key is not secure enough. Therefore, in our design we secure the key, which is a grey image using RSA algorithm. In this paper, FPGA implementation of 1024 bit RSA encryption and decryption is presented. For encryption, computation of modular exponentiation for 1024 bit size with accuracy and efficiency is needed and it is carried out by repeated modular multiplication technique. For decryption, L-R binary approach is used which deploys modular multiplication module. Efficiency in our design is achieved in terms of throughput/area ratio as compared to existing implementations. QR codes security is demonstrated by deploying AES-RSA hybrid design in Xilinx System Generator(XSG). XSG helps in hardware co-simulation and reduces the difficulty in structural design. Further, to ensure efficient encryption of the shared key by RSA, histograms of the images of key before and after encryption are generated and analysed for strength of encryption.

A hybrid approach to emotion recognition system using multi-discriminant analysis & k-nearest neighbour

Emotion recognition system using electrocardiogram (ECG) has received considerable attention recently in the area of human computer interaction (HCI). Our work in this paper is an attempt towards developing an emotion recognition system that would classify emotions effectively into four emotional states: joy, anger, sadness and pleasure. The contributions of this paper is summarized in three fold: Firstly, we extract statistical features through digital filter. Secondly, to extract spectral features such as power and entropy features, we decompose and reconstruct the ECG signal through empirical mode decomposition (EMD) and apply Hilbert huang transform (HHT) as well as discrete fourier transform (DFT) to the intrinsic mode functions (IMFs). Finally, the effectiveness of our proposed hybrid scheme is demonstrated through experimental results in terms of various performance measures.