Anurag Mahajan

Area- and Power-Efficient Architecture for High-Throughput Implementation of Lifting 2-D DWT

We have suggested a new data-access scheme for the computation of lifting two-dimensional (2-D) discrete wavelet transform (DWT) without using data transposition. We have derived a linear systolic array directly from the dependence graph (DG) and a 2-D systolic array from a suitably segmented DG for parallel and pipeline implementation of 1-D DWT. These two systolic arrays are used as building blocks to derive the proposed transposition-free structure for lifting 2-D DWT. The proposed structure requires only a small on-chip memory of (4N + 8P) words and processes a block of P samples in every cycle, where N is the image width. Moreover, it has small output latency of nine cycles and does not require control signals which are commonly used in most of the existing DWT structures. Compared with the best of the existing high-throughput structures, the proposed structure requires the same arithmetic resources but involves 1.5N less on-chip memory and offers the same throughput rate. ASIC synthesis result shows that the proposed structure for block size 8 and image size 512 512 involves 28% less area, 35% less area-delay product, and 27% less energy per image than the best of the corresponding existing structures. Apart from that, the proposed structure is regular and modular; and it can be easily configured for different block sizes.

Implementation of low power FFT structure using a method based on conditionally coded blocks

This paper proposes a coding technique which reduces switching activity hence power consumption in FFT structures. This technique involves a sequential creation of conditionally coded blocks in the inputs of FFT structure. These blocks are then converted to low switching activity blocks using the proposed technique and are concatenated to each other in a sequential order to produce the optimized output. To increase the efficiency, the scheme is applied recursively after each concatenation. The performance of proposed method has been tested and it was found that with respect to 2s complement, the average switching activity is reduced by 38% for different bus lengths. The significant reduction in switching activity leads to power savings of 35% for a 16-bit bus. The hardware, used for encoding and decoding purposes, has been designed using Magma© tools.

Scheduling-scheme and parallel structure for multi-level lifting two-dimensional discrete wavelet transform without using frame-buffer

In this paper, we have proposed a novel scheduling scheme for generating continuous input-blocks for the succeeding processing units of parallel structure to achieve 100% hardware utilisation efficiency (HUE) without block folding. Based on the proposed scheme, we have derived a parallel and pipeline structure for multilevel lifting two-dimensional discrete wavelet transform (DWT). The proposed structure involves regular data-flow and does not require frame-buffer, and calculates DWT levels concurrently. A theoretical comparison shows that the proposed structure for J = 2 involves 1.25 times more multipliers and adders, 2 N more registers than those of existing folded block-based structure and offers 1.25 times higher throughput, where N is the input-image width. Compared with similar existing parallel structure, the proposed structure requires the same number of multipliers and adders, 2.125 N less registers and offers the same throughput rate. Application specific integrated circuit synthesis result shows that the core of the proposed structure for 2-level DWT and image size (512 × 512) involves 41% less area-delay-product and 36% less energy-per-image than those of similar existing parallel structure.

Efficient VLSI architecture for implementation of 1-D discrete wavelet transform based on distributed arithmetic

In this paper we have proposed DA based architecture for computation of one-dimensional (1-D) discrete wavelet transform (DWT). Carry-save full-adder (CSFA) and carry-save-accumulator are used to reduce critical path delay of the proposed structure. The structure has small bit-clock period Tb=max (TMR, TFA), where TMR is the ROM memory read time and TFA is full-adder gate-delay. Compared with best of the existing designs, the proposed structure involves significantly less hardware resource and offers higher throughput rate than other. Xilinx simulation result shows that, proposed structure involves 1.6 times less slices than the best of the available design and offers 1.45 times higher throughput rate. It involves significantly less area-delay product than the other. The proposed structure may be used for low-complexity and high-speed implementation of 1-D DWT for resource constrained multimedia applications.

An efficient VLSI architecture for iterative logarithmic multiplier

Logarithmic Number System (LNS) based multiplier plays a significant role in the fields of Digital Signal Processing (DSP), Image processing and Neural network which needs a lot of arithmetic operation. In all arithmetic operations, the multiplication is most hardware consuming component. Here, we give a possible solution to that problem by using an efficient VLSI architecture of Mitchells algorithm based iterative logarithmic multiplier with seamless pipelined technique. The proposed work is based on the hardware minimization at the same error cost than of previously reported architectures. We use VHDL to design the existing and proposed Mitchells algorithm based iterative logarithmic multiplier. Both multipliers design are evaluated with the Synopsys design compiler by using 90 nm CMOS technology and compared the results in terms of Data Arrival Time (DAT), Area, Power, Area Delay Product (ADP), and EPS (Energy per Sample). The proposed design involves 30.99 %, 31.10 %, and 20.84 % ADP, 5.12 %, 15.48%, and 23.55 % less EPS in comparisons of existing Mitchells algorithm based iterative logarithmic multiplier for 8 bit, 16 bit, and 32 bit operations respectively.

Implementation of Leading One Detector based on Reversible Logic for Logarithmic Arithmetic

Nowadays computers are more efficient and more complex than their predecessors. But, there is some penalty of each and every advantage in the field of technology. Here, penalty comes in terms of power consumption. According to Moore’s law, primary reasons for the rise in power consumption are the increase in clock frequency and the increased number of transistors packed onto in same die area. Reversible logic provides high speed and less power consumption. So, it has been widely used in designing of digital circuits for low-power and high-speed computation. Design of Leading One Detector (LOD) is an important circuit as they are used for the normalization process in floating point multiplication, logarithmic multiplication, and in logarithmic converters as useful components. In this paper, we designed a novel LOD based on reversible logic. In order to construct leading-one detector, the innovative reversible Feynman gate (FG) and a special case of TKS gate are proposed. The 4-bit, 8-bit, 16-bit and 32-bit LOD are designed based on the above blocks and some existing reversible gates. VHDL programmed for LOD have been modeled. According to the simulation results, our circuit’s logic structures are validated. In terms of Ancillary inputs, garbage outputs quantum cost and delay