Sang-Bock Cho

Ferroelectric Properties of La Doped Na1/2Bi1/2TiO3 (NBT) Lead-Free Ferroelectric Ceramics

La doped Na 1/2 Bi 1/2 TiO3 (NBT), Na 1/2 Bi1/2 − xLaxTiO3 (NBLT; x = 0, 0.01, 0.03, 0.05, 0.07, 0.10) ceramics, were prepared by solid-state reaction method. The effect of La doping on dielectric and ferroelectric properties of lead free NBT ferroelectric ceramics were investigated. NBT and NBLT single-phase were confirmed by X-ray diffraction. The La doping was influenced the dielectric behavior and ferroelectric property. With increasing La doping, the dielectric peak of phase transition becomes broaden and the peak disappeared up to x = 0.07. The ferroelectric P-E hysteresis loop changed from a leaky shape to slim shape.

Design of smart piezoresistive pressure sensor

A silicon piezo-resistive smart pressure sensor is designed for implementation with a 0.6 /spl mu/m double poly double metal CMOS process. This smart sensor is composed of a diaphragm with piezoresistive resistors, Wheatstone bridge and circuitry composed of op-amp, A/D converter and UART. The relationship between the bridge output voltage and the mechanical stress due to pressure was studied by simulating the stress distribution on the diaphragm with the COSMOS-M package program. The CMOS op-amp circuit was designed with different transistor sizes to obtain the defined output characteristics and simulated with HSPICE. The A/D converter was designed using a neuron MOSFET structure and a sub-ranging method to minimize the chip area. The UART circuit was designed using VHDL source code and cell library by synthesizing with Synopsys, and the physical layout of the circuit is designed with Mentor tools. The temperature compensation and output-offset problem are to be studied further.

Low phase noise and Fast locking PLL Frequency Synthesizer for a 915MHz ISM Band

In this paper, Low phase noise and Fast locking PLL Frequency Synthesizer in a 0.18-um CMOS process is presented. This thesis application is the 915MHz ISM band wireless transponder upon the CPFSK (Continuous Phase Frequency Shift Keying) modulation scheme. Frequency synthesizer designs based upon self-biased techniques are presented. The PLL frequency synthesizer designs achieve process technology independence, fixed damping factor fixed bandwidth to operating frequency ratio, broad frequency range, input phase offset cancellation, and , most importantly. A fully-integrated, 915M ISM band wireless transponder using CPFSK communication, frequency synthesizer in the frequency range of 320M ~ 960MHz with frequency resolution of 10MHz, is designed in 0.18 mum CMOS process and silicon performance is measured. Integer-N architecture is chosen for implementation. It consumes 20 mW of power at 1.8V supply and core area is 540mum times 450mum. The measured phase-noises are -117.92dBc/Hz at 10MHz offset, respectively, with low settling time less than 3.3 mus.

Development of hybrid electrical model for CNT based Through Silicon Vias

This paper presents a hybrid electrical model of Carbon nanotube (CNT) based Through Silicon Via (TSV) using Metal Oxide Semiconductor (MOS) structural approach which takes into account factors such as substrate doping, operational frequency and voltage transmission levels. The MOS structural approach considers the CNT-based TSVs as a metal-oxide-semiconductor device, thereby resulting in a depletion capacitance which reduces the overall TSV capacitance. This affects the electrical performance of CNT-based TSVs, but has been ignored in previous models. Evaluation of electrical performance has been performed through S-parameter simulation of TSV and the simulation results have been compared with previously published electrical models of CNT-based TSV. The proposed hybrid electrical model shows CNT-based TSV better performance when compared with other published models.

An efficient built-in self-test algorithm for neighborhood pattern sensitive faults in high-density memories

As the density of memories increases, unwanted interference between cells is increased and testing high density memories for a high degree of fault coverage can require either a relatively large number of test vectors or a significant amount of additional test circuitry. In this paper, a new thing method and an efficient BIST algorithm for NPSFs are proposed. Instead of the conventional five-cell and nine-cell physical neighborhood layouts to test memory cells, a four-cell layout is used. This four-cell layout requires smaller test vectors and shorter test time. A CMOS column decoder and the parallel comparator proposed by P. Mazumder and J.H. Patel are modified to implement test procedure which is appropriate for the four-cell layout. Consequently, these reduce the number of transistors used for a BIST circuit. Also, we present properties of the algorithm, such as its capability to detect stuck-at faults, transition faults, and conventional pattern sensitive faults.

FPGA implementation of stereoscopic image proceesing architecture base on the gray-scale projection

With the advance of image processing and computer vision, a stereo vision system with two cameras has become the research of interest in many areas since its ability to depth information similar to human vision. Depth map algorithm allows camera system to estimate depth. It is a computational intensive algorithm, but can be implemented with high speed on hardware due to the parallelism property. In this paper, by analyzing digital image stabilization algorithms, we propose an efficient stereoscopic image architecture which combined gray - scaled projection with Affine transformation model. We develop the architecture by describing the various computation units in hardware description language (Verliog) and synthesizing the design into a FPGA. The synthesis and experimental results show that the proposed architecture is better than traditional SAD(sum of absolute difference) based block matching algorithm in frame rate(frame/sec).

A novel TSV inductor structure for RF applications

In this paper, we present a positional analysis of a reference ground plane for Through-Silicon-Via (TSV)-based inductor implementation. A new inductor structure is proposed which uses fewer ground planes while still achieving the same functionality. Results were derived from a 3D full wave simulation performed up to 20 GHz.

An Adaptive Method for Lane Marking Detection Based on HSI Color Model

Lane marking detection is the problem of estimating the lane boundary of a road on the image captured by a camera. This paper proposed an adaptive method based on HSI color model to detect lane marking. First, we convert RGB-based image to its HSI-based image. However, HSI color model is improved by the change in the way to calculate the intensity (I) component from RGB color images. From observing the color images of the road scene in HSI color space, we utilized the limited range of color. Hence, H, S and I component are used in this method. Just simple operations, we can detect lane marking in various road images. By comparing the results of the proposed method with other methods using RGB color model and the same method in classical HSI color model which doesn’t change the intensity component, the proposed method can label the location of lane marking accurately.

Dielectric Relaxation and Electrical Properties of Lead-Free LiNbO3-Substituted Na0.5K0.5NbO3 Ferroelectric Ceramics

Na0.5K0.5NbO3 ceramics and LiNbO3-substituted Na0.5K0.5NbO3 ceramics were prepared by the solid-state reaction method. The crystallization and grain morphology of the two types of ceramics were confirmed by X-ray diffraction and atomic force microscopy studies, respectively. The 5 mol% LiNbO3 substituted Na0.5K0.5NbO3 ceramics shows well-saturated ferroelectric P-E hysteresis loops. The dielectric and electrical properties of the ceramics were investigated in the frequency range from 10 Hz to 1 MHz and the temperature range from 25°C to 600°C. Analysis of the complex impedance relaxation by the Cole-Cole plot showed one impedance relaxation for LiNbO3 substituted Na0.5K0.5NbO3. The contributions of electrical conduction in the above mentioned temperature and frequency ranges are discussed.

Modeling and Crosstalk Evaluation of 3-D TSV-Based Inductor With Ground TSV Shielding

In this paper, we present a novel through-silicon-via (TSV)-based 3-D inductor structure with ground TSV shielding for better noise performance. In addition, a circuit model is proposed for the inductor, which can reduce the simulation time over finite-element-based 3-D full-wave simulation. Rigorous 3-D full-wave simulation is performed up to 10 GHz to validate the circuit model. The ground TSV-based 3-D inductor is found to be resilient to TSV-TSV crosstalk noise compared with conventional 3-D inductors. The simulation results revealed that more than -33 dB of isolation can be achieved at 2 GHz between the 3-D inductor and the noise probe.