Sang-Geun Park

Low-Voltage Driven P-Type Polycrystalline Silicon Thin-Film Transistor Integrated Gate Driver Circuits for Low-Cost Chip-on-Glass Panel

P-type low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) integrated driver circuits are proposed for low-cost chip-on-glass (COG) panel. In order to reduce the process cost of panel, gate driver employing level-shifter, shift register and DC–DC converter is integrated by p-type polycrystalline silicon (poly-Si) TFTs. The gate drivers are composed of the level-up and level-down voltage shifters and the robust two-clock shift registers. The DC–DC converters are designed using diode-connected type charge pumps and regulators. The proposed p-type circuits were verified successfully by the simulations and the measurements.

The Stability of Oxide TFTs under Electrical Gate Bias and Monochromatic Light Illumination

We have investigated a stability of oxide TFTs (IGZO) under electrical bias and monochromatic light illumination. Under -20 V gate bias, when 650 nm monochromatic illumination with intensity of 1 mW/cm 2 was radiated, threshold voltage (Vth) was shifted by about -1.55 V while Vth was almost constant without illumination. Even though the photon energy of 650 nm is much smaller than optical band gap of oxide active layer (Eopt~3.0 eV), Vth was changed due to generation of carriers through localized state. However, under positive gate bias of 20 V, Vth was not changed with and without 650 nm light illumination. In terms of 300 nm wavelength light, Vth was shifted positively under negative bias stress and negatively under positive bias stress. It is considered that light affected not only the active layer but also the gate insulator layer.

A Study on Improving the Reliability of Polysilicon TFTs Employing Dual-Layered Gate Insulator

The reliability of polysilicon thin-film transistors (poly-Si TFTs) employing the dual-layered gate insulator was investigated. We suggested the use of the double gate insulator, which is composed of silicon oxide (SiO 2 ) and silicon nitride (SiN x ), to overcome the lower gate-oxide reliability and high leakage-current problems caused by the thin gate insulator of poly-Si TFTs. The breakdown field increased to 9 MV/cm and the leakage current decreased by up to 1 order of magnitude compared with that of TFT using the single gate insulator. Experimental results showed that the reliability of poly-Si TFTs employing the SiN x /SiO 2 gate insulator was greatly improved by the reduced charge trapping and the relatively larger thermal conductivity of the SiN x film.

New Fraction Time Annealing Method For Improving Organic Light Emitting Diode Current Stability of Hydorgenated Amorphous Silicon Thin-Film Transistor Based Active Matrix Organic Light Emitting Didode Backplane

We propose and fabricate a new hydrogenated amorphous silicon (a-Si:H) thin-film transistor (TFT) pixel employing a fraction time annealing (FTA), which can supply a negative gate bias during a fraction time of each frame rather than the entire whole frame, in order to improve the organic light emitting diode (OLED) current stability for an active matrix (AM) OLED. When an electrical bias for an initial reference current of 2 µA at 60 °C is applied to an FTA-driven pixel more than 100 h and the temperature is increased up to 60 °C rather than room temperature, the OLED current is reduced by 22% in the FTA-driven pixel, whereas it is reduced by 53% in a conventional pixel. The current stability of the proposed pixel is improved, because the applied negative bias can suppress the threshold voltage degradation of the a-Si:H TFT itself, which may be attributed to hole trapping into SiNx. The proposed fraction time annealing method can successfully suppress Vth shift of the a-Si:H TFT itself due to hole trapping into SiNx induced by negative gate bias annealing.

Effect of Drain Bias Stress on Stability of Nanocrystalline Silicon Thin Film Transistors with Various Channel Lengths

We report the electrical stability of bottom-gate nanocrystalline silicon (nc-Si) thin film transistors (TFTs) with various channel lengths under drain bias stress for the first time. As the bias stress at the drain terminal increases at a fixed gate bias, the threshold voltage (VTH) shift of the nc-Si TFTs decreases significantly. Under the drain bias stress, the VTH shift decreases with channel length. The smaller VTH shift was analyzed on the basis of the concentration of the channel charge. A high drain bias reduces the carrier concentration near the drain terminal. Also, the ratio of the depleted charges to total charges increases with decreasing channel length due to the drain bias. Thus, a short-channel TFT has a smaller normalized channel charge than a long-channel TFT. A low carrier concentration induces a small number of defect states; thus the VTH shift of a short-channel TFT is smaller than that of a long-channel TFT.

44.3: High-Aperture Ratio AMOLED Pixel Design Employing VDD Line Elimination for Reducing OLED Current Density

A new high-aperture ratio AMOLED pixel design scheme improving OLED life-time is proposed. The VDD supply line in each pixel is eliminated and the scan line supplies VDD to a pixel, thus a high-aperture ratio of emission area is considerably increased. The increased emission area achieves a lower current density through OLED, so that the OLED degradation would be suppressed and the life-time of OLED may be improved without varying the OLED materials. We also designed a storage capacitor employing the bank layer dielectric between ITO and cathode rather than typically used VDD line.

P‐18: Highly Stable Amorphous Silicon Thin Film Transistor AMOLED Panel Employing Optical Feedback Compensation Pixel Circuit

The optical feedback scheme can compensate the threshold voltage variation of TFT and OLED as well as the degradation of OLED efficiency. The new optical feedback pixel circuit integrating a-Si:H TFT photo sensor which is designed with the reversed diode-connected TFT is proposed and fabricated. We have fabricated the 0.85 inch AMOLED panels (56 pixels × 84 pixels) employing the new optical feedback pixel circuits. The luminance degradation of AMOLED panel employing the proposed pixel after 12 hours chess board patterned stress is less than 12%, while the conventional one has 37% of luminance degradation.

Suppression of Leakage Current in Solid-Phase Crystallization Silicon Thin-Film Transistors Employing Off-State-Bias Annealing

We have fabricated p-channel metal oxide semiconductor (PMOS) solid-phase crystallization silicon (SPC-Si) thin-film transistors (TFTs) employing an alternating magnetic field on a glass substrate, which exhibit better current uniformity than excimer-laser annealed low-temperature polycrystalline silicon (ELA LTPS) TFTs, and superior stability to hydrogenated amorphous silicon (a-Si:H) TFTs. The leakage current of the SPC-Si TFT was larger than that of an a-Si:H TFT and an ELA poly-Si TFT owing to its many grain boundaries. The leakage current of the SPC-Si TFT was successfully suppressed through off-state-bias annealing. Off-state-bias annealing forced electron carriers to be trapped in the gate insulator, thus reducing the gate–drain field and suppressing the leakage current of the SPC-Si TFT. Our experimental result showed that the trapped electron charges in the gate insulator did not escape under thermal annealing or AC-bias stress. The off-state-bias annealed PMOS SPC-Si TFT could be a suitable pixel element for high-quality display applications employing an alternating magnetic field.

Ink-Jet Printed 6,13-bis (triisopropylsilylethynyl) Pentacene Organic Thin-Film Transistors for Particle Based Electronic Papers

Ink-jet printed 6,13-bis(triisopropylsilylethynyl) (TIPS) pentacene organic thin-film transistors (OTFTs) were fabricated for particlebased electronic papers. As source and drain electrode, a transparent conductive oxide, indium-tin-oxide (ITO) has been employed instead of using Au electrode. Using the ITO electrode, field-effect mobility of 0.06 cm/Vs has achieved by improving the contact between the ITO electrode and the organic semiconductor layer. For contact treatment, a combination of O2 plasma treatment and 4-chlorophenyl dichlorophosphate treatment have been used. With the OTFTs employing ITO source/drain electrode, a particlebased electronic paper array was fabricated.

Investigation of the hysteresis phenomenon of an a‐Si:H TFT at an elevated temperature for AMOLED displays

— The temperature dependence of the hysteresis of an a-Si:H TFT has been investigated. An a-Si:H TFT pixel driving scheme has been proposed and investigated. This scheme can eliminate changes in the organic light-emitting diode (OLED) current caused by hysteresis of an a-Si:H TFT. The VTH of the a-Si:H TFT was changed according to the gate-voltage sweep direction because of the hysteresis of the a-Si:H TFT. The variation of VTH for a a-Si:H TFT decreased from 0.41 to 0.17 V at an elevated temperature of 60°C because the sub-threshold slope (s-slope) of the a-Si:H TFT, in the reverse voltage sweep direction, increased more than in the forward voltage sweep direction due to a greater increase in the initial electron trapped charges than the hole charges. Although the OLED current variation caused by hysteresis decreased (∼14%) as the temperature increased, the error in the OLED current needed to be improved in order to drive the pixel circuit of AMOLED displays. The proposed pixel circuit can apply the reset voltage (−10 V) before the data voltage for the present frame that was written to fix the sweep direction of the data voltage. The variation in the OLED current caused by hysteresis of the a-Si:H TFT was eliminated by the fixed voltage sweep direction in the proposed pixel circuit regardless of operating temperature.