Sang-Heung Lee

Polycrystalline silicon-germanium heating layer for phase-change memory applications

This letter reports on the performance improvement of phase-change memory (PCM) cells by applying silicon-germanium (SiGe) alloys as resistive heating layers. The in situ doped polycrystalline Si0.75Ge0.25 films, lying under holes filled with a Ge2Sb2Te5 (GST) phase-change material in a pore-style configuration, promoted the temperature rise and phase transition in the GST. The SiGe heating layer caused drastic reduction in both set and reset currents compared to a conventional TiN heater material. The threshold voltages of the PCM cells were almost uniform irrespective of the kind of heating layers. It is considered that this beneficial effect of the SiGe heating layer originates from the high electrical resistivity and low thermal conductivity of a SiGe alloy.

Low power and high speed phase-change memory devices with silicon-germanium heating layers

The switching speed and the reliability of the phase-change memory (PCM) device employing a SiGe film as a heating layer were compared with those of the control device employing a conventional TiN heating layer. The influence of the semiconducting nature of the SiGe film on PCM operation was investigated. The critical pulse width for the onset of a set process was reduced to less than about 50% by substitution of SiGe for TiN. The cycling endurance value for the PCM device with a SiGe heating layer was comparable to that of the control device, which indicated that the introduction of a SiGe film did not induce reliability degradation. The heterojunction between the GeSbTe and SiGe layers was so leaky that the effect of the semiconduction type of SiGe was negligible. The reset current was saturated at a minimum value with increasing resistivity of a SiGe film, which was attributed to the resistance lowering of SiGe at high temperature. The PCM device with a SiGe heating layer was successively fabricated us...

The behavior of Ti silicidation on Si/SiGe/Si base and its effect on base resistance and fmax in SiGe hetero-junction bipolar transistors

The relation between Ti silicidation and base resistance in SiGe hetero-junction bipolar transistors (HBT) was investigated. The Ti layer deposited on the Si/SiGe/Si base converted to Ti silicide during two-step annealing. The thickness of the Ti silicide, which was identified as the Ti(Si1-xGex) phase of uniform composition, abruptly increased over the annealing temperature of 650/850 °C, and as a result it accomplished a very low extrinsic base resistance. The Ti silicidation affected the base resistance of real devices (RB), which was extracted from simulating the electrical data of SiGe HBTs such as I –V curves, forward Gummel plots, forward current gain curves, and s-parameter plots. It was shown that the RB was compatible with the theoretical relation which included the small-signal unity-gain frequency (fT), the maximum oscillation frequency (fmax) and RB. fmax varied more sensitively with RB than fT, which was due to the inherent property of fmax being inversely proportional to √RB. The fmax of the SiGe HBT reached 47.4 GHz when Ti silicidation was performed at the annealing temperature of 650/850 °C. This silicidation condition is thought to be an appropriate temperature for Ti silicidation applicable to SiGe HBT fabrication.

A 5.8 GHz mixer using SiGe HBT process

DSRC provides high speed radio link between Road Side Equipment and On-Board Equipment within the narrow communication area. In this paper, a 5.8 GHz down-conversion mixer for DSRC communication system is designed and fabricated using 0.8 ¿m SiGe HBT process technology and RF/LO matching circuits, RF/LO input balun circuits and IF output balun circuit are all integrated on chip. The measured performance is 7.5 dB conversion gain, ¿2.5 dBm input IP3, 46 dB LO to RF isolation, 56 dB LO to IF isolation, current consumption of 21 mA for 3.0 V supply voltage and the chip size of fabricated mixer is 1.9 mm × 1.3 mm.

Cost Effective Parallel-branch Spiral Inductor with Enhanced Quality Factor and Resonance Frequency

In this paper, we present a cost effective parallel-branch spiral inductor with enhanced quality factor and resonance frequency. This structure is designed to improve the quality factor, but different from other fully stacked spiral inductors. The parallel-branch effect is increased by overlapping the first metal below the second metal with same direction. Measurement result shows an increased quality factor of 12% improvement. Also, we show an octagonal parallel-branch inductor which reduces parasitic capacitances for higher frequency applications

A 15-GHz 7-channel SiGe:C PLL for 60-GHz WPAN Application

In this paper, we present the design of 15-GHz frequency synthesizer for 60-GHz WPAN. The PLL generates 7 channels of output signals with 250 MHz step by using the highspeed programmable divider operating up to 10 GHz. A double cross-coupled LC VCO is used for achieving higher oscillation frequency and shows about 20 % tuning range. The PLL represents phase noise of -88 dBc/Hz at 1 MHz offset from 15.75 GHz and consumes 115 mA at 2.5 V supply voltage. The PLL occupies 0.7 times 0.8 mm2 area and is fabricated using 0.25 mum SiGe:C BiCMOS process technology.

A packaged. 2.3 GHz SiGe VCO with parallel-branch inductors

In this paper, a 2.3 GHz VCO with parallel-branch inductors was designed and fabricated using 0.8-/spl mu/m SiGe HBT process technology. Their Q-factors were higher than those of the conventional inductors. A good phase noise of -122 dBc/Hz was measured at 4 MHz offset frequency, and harmonics were suppressed by -28 dBc. The manufactured VCO core consumed 3.7 mA at 2 V supply voltage, and the VCO occupied 1.8 mm /spl times/ 1.2 mm chip areas.In this paper, a 2.3 GHz VCO with parallel-branch inductors was designed and fabricated using a 0.8-/spl mu/m SiGe HBT process technology. Their Q-factors were higher than those of the conventional inductors. A good phase noise of -122 dBc/Hz was measured at 4 MHz offset frequency, and harmonics were suppressed by -28 dBc. The manufactured VCO core consumed 3.7 mA at 2 V supply voltage, and the VCO occupied 1.8 mm /spl times/ 1.2 mm chip area.

A 45-to-60-GHz Two-Band SiGe: C VCO for Millimeter-Wave Applications

A 45 - 60-GHz two-band double cross-coupled differential VCO is designed and fabricated using 0.25 mum SiG:C BiCMOS process technology whose fmax is greater than 200 GHz. The VCO provides tuning ranges of 44.9 - 48.9 GHz when its bias current is 13 mA and of 58 - 60.4 GHz when a bias current of 7 mA draws into the VCO. The phase noises of the VCO are measured as - 99 dBc/Hz from 48.86 GHz and - 93 dBc/Hz from 60.32 GHz, at 10 MHz offset, respectively. The VCO shows moderate FOMs of 156 dBc at 60.32 GHz and 158 dBc at 48.86 GHz.

A 3.8-5.5-GHz Multi-Band CMOS Frequency Synthesizer for WPAN/WLAN Applications

In this paper, we present a 3.8-5.5 GHz multi-band CMOS frequency synthesizer for WLAN and UWB applications. In the multi-band frequency synthesizer, both new multi-mode prescaler and adaptive multi-band LC VCO are proposed. The proposed multi-mode prescaler produces six modes of divide-by-2/3, 4/5, 8/9, 16/17, 32/33, and 64/65. In the adaptive multi-band LC VCO, the gate width of cross-coupled MOS array is tuned to calibrate oscillation amplitude and alleviate 1/f flicker noise of MOS. The multi-band frequency synthesizer represents -121 dBc/Hz at 5 MHz offset from 5.24 GHz carrier. The multi-band frequency synthesizer consumes a total current of 26mA at 1.2 V, and is manufactured in 0.13-mum CMOS process technology

A 1-6 GHz monolithic up-conversion mixer with input/output active baluns using SiGe HBT process

In this paper, a 1-6 GHz MMIC up-conversion mixer, for an RF transmitter, is designed and fabricated using 0.8 /spl mu/m SiGe HBT process technology. This mixer is implemented on-chip using LO/RF wideband matching circuits, LO/IF input balun circuits, and an RF output balun circuit. The measured results of the fabricated mixer show positive power conversion gain from 1 GHz to 6 GHz, bandwidth of 4.5 GHz, LO isolation (LO to IF isolation and LO to RF isolation) between 27 dB and 45 dB, OIP3 between -2 dBm and -12 dBm, current consumption of 29 mA for 3.0 V supply voltage. The chip size of the fabricated mixer is 2.7 mm/spl times/1.6 mm.