Sang-Ho Kam

A New Wideband Distributed Doherty Amplifier for WCDMA Repeater Applications

A new wideband distributed Doherty amplifier (WDDA) for wideband code division multiple access (WCDMA) repeater applications is reported. The distributed structure provides wideband performance while not needing an N-way splitter and combiner. The two-stage Doherty amplifiers achieve high gain and high efficiency. Also, the linearity of the WDDA is improved by the post-distortion using gate bias optimization of the Doherty amplifiers. For verification, the proposed WDDA is implemented using GaN HEMTs and tested with a one-carrier WCDMA signal at 2.14 GHz. From the measured results at an average output power of 36 dBm (10 dB back-off power), the WDDA shows an adjacent channel leakage ratio (ACLR) of - 45 dBc at plusmn 5 MHz offset with a total gain over 24 dB and a total power-added efficiency over 15% over a 160 MHz bandwidth.

Design of Highly Efficient Three-Stage Inverted Doherty Power Amplifier

This letter reports the highly efficient three-stage inverted Doherty power amplifier (IDPA) using 30 W and 50 W Si LDMOSFETs. The characteristic impedances of the output combiner are derived to achieve high efficiency at a large back-off power (BOP). The output matching networks and offset lines of the carrier and peaking cells are used to modulate the load impedance. The transmission line in the input path of the carrier cell is inserted to adjust the delay among the carrier and peaking cells. The drain efficiency (DE) of 40.3% with a gain of 9 dB is achieved at output power of 42 dBm (8.5 dB BOP) and the DE above 40% is maintained in wide output range for a 2.14 GHz continuous wave signal. For a one-carrier WCDMA signal at an output power of 40 dBm (10.5 dB BOP), the DE of 35% with the gain of 9.2 dB is achieved.

A Highly Efficient Three-Stage Doherty Power Amplifier with Flat Gain for WCDMA Applications

A three-stage Doherty power amplifier (DPA) with a flat gain is represented. The driving amplifier at an input of peaking cells is used to achieve high efficiency and flat gain to control the input power level of peaking cells. For the experimental validation, the proposed DPA is implemented using a GaN HEMT and Si LDMOSFETs. For a continuous wave signal, power-added efficiencies of 34.0% and 39.3% are obtained at 8.5-dB back-off power (BOP) and 4.0-dB BOP from the saturation output power, respectively. The measured one-carrier wideband code division multiple access results show high efficiency and flat gain characteristics above 10 dB over the entire output power range.

A High-Efficiency GaN-Based Power Amplifier Employing Inverse Class-E Topology

A high efficiency, GaN based power amplifier (PA) employing the inverse class-E topology is reported. The parasitic inductance and large output capacitance of the packaged active device are used as the series inductance and compensated by a shunt inductor, respectively. The composite right/left-handed transmission line is used as a harmonic control network. For the experimental validation, an inverse class-E PA is designed using a GaN HEMT and tested with a continuous wave at 1 GHz. From the measured results, the drain efficiency and power-added efficiency (PAE) of 79.7% and 78.8% with a gain of 19.03 dB is achieved at an output power of 41.03 dBm. Also, the inverse class-E PA can deliver the output power and PAE of over 40.8 dBm and 65% through the bandwidth of 100 MHz.

Highly linear and efficient asymmetrical Doherty power amplifiers with adaptively bias-controlled predistortion drivers

A highly linear and efficient asymmetrical Doherty power amplifier (ADPA) with adaptively bias-controlled predistortion drivers (PDDs) is represented for 2.14-GHz wide-band code division multiple access (WCDMA) repeater systems. The ADPA shows the extended efficiency range by using unequal saturation powers of the main carrier and peaking cells. The driving carrier and peaking cells are used as the PDDs with the adaptive gate bias control to improve the linearity of the ADPA. To verify the proposed method, two 2-W GaN HEMTs and two 20-W GaN HEMTs are used as the driving and main cells, respectively. For a one-carrier WCDMA signal, the ADPA with PDDs produces an adjacent channel leakage ratio (ACLR) of −51.5 dBc with a total drain efficiency of 27.9% and a total gain of 28.7 dB by adaptively controlling the gate biases of PDDs. For the asymmetrical class-F DPA with PDDs, an ACLR of −38.2 dBc is achieved the total drain efficiency of 37.2 % and a total gain of 26.5 dB.

A High-Linearity Wideband Power Amplifier With Cascaded Third-Order Analog Predistorters

A high-linearity wideband analog predistortion power amplifier (PA) is presented. The memory effects of the PA are reduced by a high drain bias voltage as well as a wide bias line and several decoupling capacitors. The simple cascaded third-order analog predistorters (CTAPDs) are used to cancel the third- and fifth-order intermodulations (IM3s and IM5s) of the low-memory PA. For verification, the 45 W class-AB PA is implemented and tested using a two-tone signal and a four-carrier wideband code division multiple access (WCDMA) signals at 2.14 GHz. From the measured results, the low-memory PA with the CTAPDs delivers significant IM3 and IM5 cancellation and superior ACLR improvement.

Split augmented Hammerstein behavioral model with additional distortion path

This paper proposes the split augmented Hammerstein (SAH) model with an additional distortion path. The error signal between the source signal and the output signal of the augmented Hammerstein (AH) model is employed to enhance the accuracy of the AH model. The 13th memoryless polynomial and a finite impulse response (FIR) filter are used in the memoryless and memory effect subsystems, respectively. The coefficients of FIR filters are obtained by the recursive least square algorithm. To validate the performance of the SAH model, the Doherty power amplifier and a 2-FA WCDMA signal with 10-MHz carrier spacing at 2.14 GHz are employed. The validation results demonstrate that the SAH model can characterize the memory effects as well as the nonlinearity more accurately than the AH model.

Advanced design of a double Doherty power amplifier with a flat efficiency range

This paper reports a new double Doherty power amplifier (DDPA) with a flat efficiency range, which consists of two-stage amplifiers. When the two-way DPA is used as the main peaking amplifier, the driving peaking cell with class-C bias turns the DPA off before the saturation of the main carrier amplifier. Three efficiency-peaking points are achieved with the additional Doherty operation by the main peaking amplifier after the saturation of the main carrier amplifier. For verifications, the driving and main amplifiers are designed and implemented with 2-W and 10-W GaN HEMTs, respectively, at 2.14 GHz. From the continuous wave (CW) results, three efficiency-peaking points are obtained at approximately 9-, 5-, and 0-dB back-off powers with over 42% drain efficiency. For one-carrier wide-band code division multiple access (WCDMA) signal, the DDPA shows good digital predistortion linearization performance.

A Transistor-Based Analog Predistorter With Unequal Delays for Memory Compensation

A transistor-based analog predistorter (APD) with memory effect compensation is represented. The nonlinearity of a gain amplifier generated by a low supply voltage is used as an error generator. The predistorted signal by the unequal-delayed nonlinear paths improves the linearity by compensating for memory effects of the power amplifier (PA). For verification, the proposed APD with three-branch nonlinear paths is implemented with a 30-W class-AB PA and tested using two-tone and various wideband code division multiple access (WCDMA) signals at 2.14 GHz. From the measured results, the proposed APD significantly improves the linearity of the PA with memory effects.

Highly efficient three-stage Doherty power amplifier with adaptive driving amplifier for 3.5 GHz WiMAX applications

This paper describes a new three-stage Doherty power amplifier (DPA) with an adaptive driving amplifier inserted at the input of the carrier cell. This driving amplifier controls the input power of the carrier cell to eliminate the gate leakage current at high input power levels. Using an envelope tracking technique, the gate bias voltage of the driving amplifier is adjusted according to the input power levels. For verification, the driving amplifier, carrier, and peaking cells are fabricated using 10-W, 15-W, and 35-W GaN HEMTs, respectively, at 3.5 GHz. For a continuous wave signal, total drain efficiencies (DEs) of 37.3% and 45.6% are achieved at approximately 9.5- and 4.3-dB back-off powers (BOPs), respectively. For a worldwide interoperability for microwave access (WiMAX) signal, the proposed DPA has a total DE of 39.5 % at an 8-dB BOP.