Yoon-Ha Jeong

Study on a Scaling Length Model for Tapered Tri-Gate FinFET Based on 3-D Simulation and Analytical Analysis

A compact scaling length model for tapered Tri-gate fin field-effect transistors (FinFETs) is presented based on a 3-D simulation and an analytic potential model. Short-channel effects (SCEs) of rectangular FinFETs can be controlled by designing the fin width, fin height, and gate length to satisfy scaling theory. Tapered FinFETs have a fin top width shorter than the fin bottom width, and they show a different dependence of subthreshold behaviors and SCEs compared to rectangular FinFETs. The proposed scaling length model for tapered FinFETs, expressed as a function of fin bottom width, fin height, and tapering angle, is presented based on the 3-D Poissons equation and a non-Cartesian mesh. The dependence of the subthreshold behaviors of tapered FinFETs calculated with the proposed model is compared with that of rectangular FinFETs. We found that longer fin bottom widths and fin heights of tapered FinFETs can be designed by applying the proposed scaling length model for the scaling parameter.

Statistical variability study of random dopant fluctuation on gate-all-around inversion-mode silicon nanowire field-effect transistors

Random dopant fluctuation effects of gate-all-around inversion-mode silicon nanowire field-effect transistors (FETs) with different diameters and extension lengths are investigated. The nanowire FETs with smaller diameter and longer extension length reduce average values and variations of subthreshold swing and drain-induced barrier lowering, thus improving short channel immunity. Relative variations of the drain currents increase as the diameter decreases because of decreased current drivability from narrower channel cross-sections. Absolute variations of the drain currents decrease critically as the extension length increases due to decreasing the number of arsenic dopants penetrating into the channel region. To understand variability origins of the drain currents, variations of source/drain series resistance and low-field mobility are investigated. All these two parameters affect the variations of the drain currents concurrently. The nanowire FETs having extension lengths sufficient to prevent dopant p...

Improved Electrical Characteristics of Honeycomb Nanowire ISFETs

Ion-sensitive field-effect transistors (ISFETs) with a honeycomb nanowire (HCNW) structure have been fabricated on a silicon-on-insulator wafer. The HCNW ISFET shows lower threshold voltage, lower subthreshold swing, higher drain current, and lower variability than the conventional nanowire device. Improved electrical characteristics are mainly due to the increased effective channel width and enhanced current drivability. The HCNW structure also exhibits improved current sensitivity in its pH response. These results suggest that the HCNW structure is promising for enhancing device performance and realizing sensors with high sensitivity.

Vertical gate-all-around junctionless nanowire transistors with asymmetric diameters and underlap lengths

Vertical gate-all-around (GAA) junctionless nanowire transistors (JNTs) with different diameters and underlap lengths are investigated using three-dimensional device simulations. The source-side diameter determines the on-current and drain-induced barrier lowering characteristics, whereas the drain-side diameter controls the band-to-band tunneling current during off-state conditions. The JNTs with short drain-side underlap lengths decrease the source/drain series resistance but increase the off-current values, especially due to large band-gap narrowing effects at the drain extension region. Proper device design of vertical GAA JNTs considering the device structure and underlap is needed to improve both on/off and short channel characteristics.

Junction Design Strategy for Si Bulk FinFETs for System-on-Chip Applications Down to the 7-nm Node

DC/AC characteristics of Si bulk FinFETs including middle-of-line levels are precisely investigated using well-calibrated 3-D device simulations for system-on-chip applications. Scaling the fin widths down to 5 nm effectively enhances gate-to-channel controllability and improves RC delay, but a dramatic increase in band-to-band tunneling currents from source-to-drain does not satisfy low-power application in the 7-nm node. All lightly-doped extension regions as a solution could improve band-to-band tunneling currents and total gate capacitances because of better short-channel immunity and lower parasitic capacitances, respectively. Using systematic TCAD-based RC calculation, we suggest optimized overlap/underlap lengths in the 7-nm node FinFETs to overcome the scaling limitations.

Investigation of the electrical stability of Si-nanowire biologically sensitive field-effect transistors with embedded Ag/AgCl pseudo reference electrode

We report on the electrical stability of Si-nanowire biologically sensitive field-effect transistors (BioFETs) fabricated using conventional microfabrication technique, with an embedded Ag/AgCl pseudo-reference electrode (pRE) formed by an electrochemical method. The open-circuit potential (OCP) characteristics between the pRE and a commercial reference electrode have been measured in order to evaluate the influence of the pRE potential on the device performance. In a pH sensing mode, the fabricated pRE follows the applied potential accurately with a small offset value of below 6 mV for pH in the range of 4 to 10. The BioFET was also used for the detection of alpha fetoprotein (AFP) with a detection limit of 10 pg mL−1 and the corresponding OCP fluctuation of the pRE was less than 1.5 mV, independent of the AFP concentrations. These results suggest that the Si-NW BioFETs with the embedded Ag/AgCl pRE are very promising for reliable biosensing applications.

Simple S/D Series Resistance Extraction Method Optimized for Nanowire FETs

The conventional source/drain series resistance (<i>R</i>_sd) extraction method is not applicable to nanowire field effect transistors (NWFETs), as NWFETs have fluctuating characteristics in <i>Id</i> and there is insufficient physical modeling. In this letter, we propose a modified <i>R</i>_sd extraction method that uses an optimized <i>Id</i> equation and a threshold voltage (<i>V</i>_th) extraction procedure for NWFETs. The <i>Id</i> equation is modified for the geometry of the NWFET, and <i>V</i>_th is obtained from the linear Y-function that can be observed in NWFETs because of volume inversion. A necessary assumption for this procedure is experimentally confirmed using the Y-function, and equations that fit the measured data perform well; this justifies the validity of applying the modified <i>Id</i> equations to NWFETs. Therefore, <i>R</i>_sd is perfectly extracted in all NWFETs and it is observed to be dependent on the channel diameter (<i>d</i>_NW) when normalized by <i>d</i>_NW, indicating that the extension resistance is the dominant component in the total <i>R</i>_sd.

Impact of the spacer dielectric constant on parasitic RC and design guidelines to optimize DC/AC performance in 10-nm-node Si-nanowire FETs

In this paper, we propose an optimized design for Si-nanowire FETs in terms of spacer dielectric constant (κsp), extension length (LEXT), nanowire diameter (Dnw), and operation voltage (VDD) for the sub-10 nm technology node. Using well-calibrated TCAD simulations and analytic RC models, we have quantitatively evaluated geometry-dependent parasitic series resistances (RSD) and capacitances (Cpara). Compared with low-κ spacers, high-κ spacers exhibit a higher on/off-current ratio with a lower RSD, but show severe degradation in their AC performance owing to a higher Cpara. Considering the trade-off between RSD and Cpara, optimal geometry-dependent κsp values at various supply voltages (VDD) are determined using gate delay (CV/I) and current-gain cutoff frequency (fT). We found that as LEXT and VDD decrease and Dnw increases, the optimal κsp value shifts from the high-κ to low-κ regime.

Investigation of Low-Frequency Noise in p-type Nanowire FETs: Effect of Switched Biasing Condition and Embedded SiGe Layer

The low-frequency noise (LFN) of a p-type nanowire FET (p-NWFET) was characterized and compared with that of an n-type NWFET (n-NWFET) in terms of dominant noise source and its location in the channel region. An inverse proportional dependence of the noise level on channel diameter was observed in the p-NWFET but not in the n-NWFET. The LFN was observed to be mainly generated by Hooge mobility fluctuation in the p-NWFET. Under a switched biasing condition, p-NWFET showed no substantial LFN reduction (in contrast to the n-NWFET), indicating that the carrier number fluctuation was insignificant. This was due to the compressive stress induced by embedded SiGe with heavier transverse effective hole mobility.

Extraction of source/drain resistivity parameters optimized for double-gate FinFETs

Source/drain series resistances (Rsd) of n- and p-type double-gate fin field-effect transistors (FinFETs) were successfully extracted using the methods applicable to short channel devices. Rsd is decomposed into spreading, sheet, and contact resistances considering top and sidewall contact resistances separately. Resistivity parameters defined in the analytic model were extracted from the extracted Rsd values of FinFETs with different fin widths and spacer lengths, and the proposed model showed good agreement to the experimental data.