Sang-Pil Sim

Physical understanding of low-field carrier mobility in silicon MOSFET inversion layer

Experimental and theoretical studies of the gate field dependencies of the low-field mobilities of electrons and holes show that by changing surface orientations and oxidation conditions the two-dimensional electron gas formulation can successfully explain eta =1/3 (where eta is the weighting factor of mobile charge density used in calculating the effective field for the universal mobility curve) for

Modeling inversion-layer carrier mobilities in all regions of MOSFET operation

Abstract Channel electron and hole mobilities in MOSFETs have been extracted in terms of the effective vertical field for several substrate biases. After ascertaining that the 2-D drift–diffusion numerical device simulator is reproducing the substrate charge variation in the MOSFET with respect to the gate voltage, obtained from C–V data, the mobility versus effective field behavior is extracted by comparing the simulated and measured Id–Vgs characteristics. A simple model has been constructed to fit the extracted mobility data in weak and strong inversion, for inversion-layer electrons and holes in n-MOSFET and p-MOSFET, respectively.

High-frequency on-chip inductance model

The effect of random signal lines on the on-chip inductance is quantitatively investigated, using an S-parameter-based methodology and a full wave solver, leading to an empirical model for high-frequency inductance. The results clearly indicate that the random signal lines as well as designated ground lines provide return paths for gigahertz-frequency signals. In particular, quasi TEM-wave-like propagation mode is observed above 10 GHz, revealing a unique relationship between capacitance and inductance of the signal line. Incorporating the random capacitive coupling effect, our frequency-dependent RLC model is confirmed to be valid up to 100 GHz.

An effective loop inductance model for general non-orthogonal interconnect with random capacitive coupling

We propose a first-ever analytic inductance model for practical on-chip interconnects with random signal lines. Validity of the effective loop inductance approach and determination of return paths through random capacitive coupling are investigated using a full-wave solver, leading to a frequency-dependent RLC model. Non-orthogonal interconnects are also investigated and included in our model.

Methodology of parameter and coupling ratio extraction for source side injection (SSI) flash cell

We present a new methodology to generate a two-transistor MACRO model of a SSI Flash cell based on a practical cell partitioning and a systematic and rigorous parameter extraction scheme. Through judicious use of TCAD simulation and precise measurement techniques, BSIM3 parameters of the individual transistors and coupling ratios of the cell were extracted, yielding a SPICE-compatible MACRO model for a three-poly split-gate Flash cell.

Tunnel Oxide Optimization to Improve Post-Cycling Retention of Flash Memories

To improve post-cycling retention of Flash memory, we present NO re-oxidation technique for tunnel oxide growing. We demonstrate that the quality of NO re-oxidation tunnel oxide is superior to that of conventional NO annealing oxide. The quality of NO re-oxidation is strongly affected by NO concentration and re-oxidation thickness. Using well-optimized NO re-oxidation, we accomplish successful operation of 512Mb NOR Flash in a 65nm technology, satisfying highly reliable retention characteristicᄂ as well. Introduction Program/erase cycling of Flash memories causes damage to the tunnel oxide in the form of neutral and charged bulk traps and interface states. When charges are detrapped, charge trapping at the interface traps and oxide bulk can cause threshold voltage shifts in post-cycling retention tests [1]. To improve the characteristic of post-cycling retention, the nitride treatments of tunnel oxide are mainly obtained by annealing the oxide in NO or N2O ambient [2], [3]. In this work, we suggest another novel method for tunnel oxide nitridation; ‘NO re-oxidation’. We demonstrate that the quality of NO re-oxidation oxide is superior to that of NO annealing oxide. Furthermore, the quality of NO re-oxidation oxide is found to be strongly affected by NO concentration and re-oxidation thickness. Experiment Devices were fabricated with 65nm NOR technologies. 10K cycles of program/erase were performed with retention bake at 200°C. Data were collected from a 512K bits array. The threshold voltage shifts due to the cycling and bake were measured in a 512K bits array. The I-V characteristics of the single cell were measured before and after the cycling stress. Results The programmed Vth dispersion (“10” and “01” states in multi-level cell) measured from 512K cells after 10K cycles and post-cycling bake are shown in Fig. 1 and Fig. 2, respectively. The Vth shifts after post-cycling bake resulting from NO re-oxidation are smaller than that from NO tunnel oxide. This can be understood in correlation with the difference in the quality of tunnel oxide. Fig. 3 shows the endurance characteristics of the cells where the program and erase operation are done by channel hot electron injection and channel F-N tunneling, respectively. The upward shift of the erase Vth of NO re-oxidation is larger compared with the NO annealing oxide. Fig. 4 shows the drain current as a function of the gate voltage for both NO annealing and NO re-oxidation oxides. The Vth shift and the sub-threshold swing degradation after endurance is smaller for the case of NO re-oxidation. Clearly, the NO re-oxidation oxide exhibits the advantages in endurance characteristics over NO anneal oxide. Fig. 5 and Fig. 6 show the endurance characteristics for NO re-oxidation in different conditions. (NO Re-Ox.(I) and NO Re-Ox.(II)). From the Id-Vg plot, the Vth shifts for NO re-oxidation are exceptionally sensitive to the growing condition. It implies that the careful engineering of the NO re-oxidation process can further improve the quality of tunnel oxide. Fig. 7 shows the post cycling retention data for different tunnel oxides, in which each point represents Vth shift (∆ VT,Lowest in Fig.1 and Fig. 2) of the worst bit in 512K bits. The ∆ VT,Lowest by NO re-oxidation is reduced compared to the normal NO annealing oxide. The improvement is even more evident for the well-optimized NO re-oxidation oxide, i.e. NO Re-Ox. (II) in Fig. 7. Fig. 8 shows the ∆ VT,Lowest as a function of the re-oxidation thickness for the samples processed with different concentration of NO ambient. The increment in re-oxidation thickness leads to significant improvement in the post cycling retention. However, the further increases the re-oxidation thickness up to the certain point, the more increases ∆ VT,Lowest in the post cycling retention. It indicates that there is an optimum thickness of the NO re-oxidation for the best retention characteristic. Moreover, increasing nitrogen incorporation in NO annealing process also ameliorates the post cycling retention. Analysis Trapped charge during endurance alters the I-V characteristics. The interface trapping can be measured by the change of the sub-threshold swing and the Vth shifts denoted by ∆ VT,Nit . If the total Vth shift after endurance is ∆ VT,total, the Vth shift by oxide bulk trap (∆ VT,Not) can be represent by ∆ VT,Not = ∆ VT,total ∆ VT,Nit. The ∆ VT,Lowest in the post cycling retention is caused by electron detrapping from interface and oxide bulk trap. Thus, the ∆ VT,Lowest is proportional to the total amount of charge trapped during cycling. Fig. 9 shows the ∆ VT,Lowest by oxide bulk traps vs. re-oxidation thickness and NO ambient. It can be seen that the Vth shift by oxide traps maintains constant value up to certain thickness, while more re-oxidation give rise to significant increasing of Vth shift. On the other hand, as shown Fig. 10, increasing re-oxidation thickness rapidly reduces the Vth shift by interface traps. These results can be explained with a two-step mechanism of NO re-oxidation [3]. First, there is an initial reaction between the incoming O2 and the nitride layer at the interface, such reaction is interface limited. Thus, increasing re-oxidation thickness can reduce interface trap only. However, with increasing the re-oxidation thickness up to certain value, the reaction between O2 and the nitride layer is ended, and the additional oxide is grown. This unwanted oxide contains many bulk trap sites, since nitrogen-related bonds replace Si-O bonds in the oxide bulk and hence weaken the oxide structure. Thus, as shown Fig. 8, we appreciate that the initial reliability improvement in region “A” is caused by the decrease of interface traps and the reliability degradation in region “B” is caused by the increase of oxide bulk traps. Fig. 11 shows the contribution portion for the Vth shifts by interface traps, oxide traps and NO concentration. As the NO concentration increases, the interface traps exponentially decrease, and then only the oxide bulk traps remains. Therefore, the oxide bulk traps are the major contributor to Vth shift. Conclusion We show that the NO re-oxidation process improves the reliability of post-cycling retention. Moreover, using optimization of NO re-oxidation, we achieve highly reliable endurance and retention characteristics in 512M NOR MLC flash memory. References [1] Neal Mielke et al, IEEE Transaction on Device and Materials Reliability, p. 335~344, 2004 [2] D. Barzzeli et al, Solid-State Electronics, p. 1271~1278, 2001 [3] C. Gerardi et al, Micron, p. 291~292, 2000 Extended Abstracts of the 2006 International Conference on Solid State Devices and Materials, Yokohama, 2006, -990F-7-5L pp. 990-991

Unified model for on-chip interconnects

In this paper, we present a compact unified model for on-chip interconnects, which includes a quasi-3D capacitance model and an effective loop inductance model. To effectively model three-dimensional fringe components in the capacitance model, we propose a novel concept of effective width for a 3D wire, which provides a physics-based approach to decompose any 3D structure into a series of 2D segments. To construct analytic and hierarchical model of loop inductance, an effective loop inductance approach is studied. In particular, we show empirically that high-frequency signal propagating through random signal lines can be approximated by a quasi-TEM mode relationship, leading to a simple way to extract the high-frequency inductance. The capacitance and inductance models are combined into a unified frequency-dependent RLC model describing successfully the wide-band characteristics of on-chip interconnects up to 100GHz. Non-orthogonal wire architecture is also investigated and included in the proposed model. Regarding coupled wire, the impact of resistance matrix on crosstalk noise is studied. The off-diagonal terms of resistance matrix are related to return path, which is important for accurate noise modeling at high frequency. It is shown that the error in crosstalk peak noise can be significant if the return path resistance is ignored.