Shoba Krishnan

Electron transport through metal-multiwall carbon nanotube interfaces

In this paper, we examine mechanisms of electron transport across the metal-carbon nanotube (CNT) interface for two different types of multiwall carbon nanotube (MWNT) architectures, horizontal or side-contacted MWNTs and vertical or end-contacted MWNTs. Horizontally aligned nanotube growth and electrical characteristics are examined with respect to their potential applications in silicon-based technologies. Recent advances in the synthesis techniques of vertical MWNTs have also enhanced the possibility for a manufacturable solution incorporating this novel material as on-chip interconnects or vias as copper interconnect feature sizes are scaled into the sub-100-nm regime. A vertical MWNT architecture is presented that may be suitable for integration into silicon-based technologies. The growth method for this architecture and its effect on electrical characteristics are examined. Through simulations, dc measurements, and comparison of our results with previous studies, we explain why high contact resistance is observed in metal-CNT-metal systems.

Characteristics of aligned carbon nanofibers for interconnect via applications

Electrical properties of plasma-enhanced chemical vapor deposited carbon nanofibers (CNFs) are characterized with measurements over a broad temperature range (4-300 K). Temperature-dependent measurements of CNF via resistivity reveal a behavior resembling the mixture of graphite a-axis and c-axis transport mechanisms. For the first time, temperature-dependent characteristics of CNFs are measured and modeled based on previously developed models for electron conduction in graphite. Reliability measurements are performed to demonstrate the robust electrical and thermal properties of CNF vias for next-generation on-chip-interconnect designs.

Test generation and concurrent error detection in current-mode A/D converters

Analog MOS circuits are becoming increasingly sophisticated in terms of checking and correcting themselves. Self-correcting, self-compensating, or self-calibrating techniques has been employed in analog-to-digital (A/D) converters to eliminate errors caused by offset and low frequency noise and cancel the error effect. For real-time applications, however, it is rather difficult to achieve validation of the converted data in the presence of faulty switching element(s). In this paper, fault behaviors and test generation of a current-mode A/D converter are addressed. Results show that the converter achieves full testability with two test currents. In addition, an A/D converter with concurrent error detection capability is proposed. The converter detects all transient faults. >

Contact resistance in carbon nanostructure via interconnects

We present an in-depth electrical characterization of contact resistance in carbon nanostructure via interconnects. Test structures designed and fabricated for via applications contain vertically aligned arrays of carbon nanofibers (CNFs) grown on a thin titanium film on silicon substrate and embedded in silicon dioxide. Current-voltage measurements are performed on single CNFs using atomic force microscope current-sensing technique. By analyzing the dependence of measured resistance on CNF diameter, we extract the CNF resistivity and the metal-CNF contact resistance.

Circuit Modeling of High-Frequency Electrical Conduction in Carbon Nanofibers

We show that the simplest possible circuit model of high-frequency electrical conduction in carbon nanofibers from 0.1 to 50 GHz is a frequency-independent resistor in parallel with a frequency-independent capacitor. The resistance is experimentally determined and represents the total dc resistance of the nanofiber and its contacts with the electrodes. The capacitance is obtained as a free parameter and has not been previously observed. The experimental method utilizes a ground-signal-ground test structure whose two-port scattering parameters (S-parameters) can be described to within plusmn0.5 dB and plusmn2deg using a simple lumped-element circuit model. The nanostructure is placed in the signal path of the test structure, and its equivalent circuit is deduced by determining what additional elements must be added to the test structure circuit model to reproduce the resulting changes in the S-parameters. This methodology is applicable to nanowires and nanotubes.

A competition-based approach for undergraduate mechatronics education using the arduino platform

This paper describes the content of an undergraduate class in mechatronics at Santa Clara University. Designing an undergraduate course in mechatronics poses a challenge as it integrates subareas in mechanics, computer science, electronics and control systems. The problem is compounded when students are from different fields of engineering and have diverse backgrounds and skills. We describe a competition-based framework that has been integrated with rigorous labs to develop skills in core areas that are needed to complete a course capstone project successfully. Students learn the basics of mechatronics and, in the project, develop a mobile robot. The project varies from year to year. Our course is based on the low-cost Arduino platform. This paper briefly discusses pedagogical strategies and tools that have been used at other schools, and then focuses on describing the lecture, laboratory, and project components of our course. The results are encouraging and indicate that our course structure provides an effective means for learning mechatronics.

Extraction of contact resistance in carbon nanofiber via interconnects with varying lengths

A method to extract the contact resistance and bulk resistivity of vertically grown carbon nanofibers (CNFs) or similar one-dimensional nanostructures is described. Using a silicon-compatible process to fabricate a terrace test structure needed for the CNF length variation, the contact resistance is extracted by measuring in situ the resistances of individual CNFs with different lengths and within a small range of diameters using a nanoprober inside a scanning electron microscope. Accurate determination of contact resistances for various combinations of catalysts and underlayer metals can lead to eventual optimization of materials’ growth and device fabrication processes for CNF via interconnects.

TEST GENERATION AND CONCURIPENT ERROR DETECTION IN CURRENT-MODE A/D CONVERTERS

Analog MOS circuits are becoming increasingly sophisticated in terms of checking and correcting themselves. Self-correcting, self-compensating, or s e v calibrating techniques have been employed in Analog-todigital (A.D) converters to eliminate errors cuased by oflset and low frequency noise, and to cancel error effect and nonlinearities. For real-time applications, howcver, it is rather dificult to achieve validation of the converted data in the presence of faulty switching element(s). In this paper, fault effects and test generation of a current-mode MD converter are addressed. Results show that the converter achieves full testability with two test currents. In addition, an A/a converter with concurrent error detection capability is proposed. The converter detects all transient faults.

An Ultralow-Power 10-Gbits/s LVDS Output Driver

This paper describes a new topology and implementation of a 10-Gbits/s low-voltage differential-signaling (LVDS) voltage-mode output driver designed for high-speed data-transfer applications. Using a positive-feedback technique, the driver achieves ultralow-power operation while maintaining the proper internal chip impedance required for matching the line impedance. As a result, signal reflection is minimized, and good signal integrity is achieved. The driver, which consists of a predriver and an output stage, consumes a total of 15.63-mW at-speed power. In measurements, the driver, which was a part of an equalizer chip, achieved a peak-to-peak jitter of 11 ps at 10 Gbits/s and a return-loss performance of less than -15 dB. It provides a single-ended output swing of 400 mV and a common-mode voltage of 1.25 V, which are compliant with LVDS standards. The chip is fabricated in a standard 2.5-V/1.2-V SiGe BiCMOS technology with 100-GHz peak ft and is packaged in a commercial LLP package.

Loop-based inductance extraction and modeling for multiconductor on-chip interconnects

An efficient extraction and modeling methodology for self and mutual inductances within multiconductors for on-chip interconnects is investigated. The method is based on physical layout considerations and current distribution on multiple return paths, leading to loop inductance and resistance. It provides a lumped circuit model suitable for timing analysis in any circuit simulator, which can represent frequency-dependent characteristics. This novel modeling methodology accurately provides the mutual inductance and resistance as well as self terms within a wide frequency range without using any fitting algorithm. Measurement results for single and coupled wires within a multiconductor system, fabricated using 0.13 and 0.18 /spl mu/m CMOS technologies, confirm the validity of the proposed method. Our methodology can be applicable to high-speed global interconnects for post-layout as well as prelayout extraction and modeling.