Sang-Won Hwang
Samsung
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Publication
Featured researches published by Sang-Won Hwang.
IEEE Journal of Solid-state Circuits | 2016
Woopyo Jeong; Jaewoo Im; Doohyun Kim; Sang-Wan Nam; Dongkyo Shim; Myung-Hoon Choi; Hyun-Jun Yoon; Dae-Han Kim; Y. Kim; Hyun Wook Park; Donghun Kwak; Sang-Won Park; Seok-Min Yoon; Wook-ghee Hahn; Jinho Ryu; Sang-Won Shim; Kyung-Tae Kang; Jeong-Don Ihm; In-Mo Kim; Doo-Sub Lee; Ji-Ho Cho; Moosung Kim; Jae-Hoon Jang; Sang-Won Hwang; Dae-Seok Byeon; Hyang-ja Yang; Kitae Park; Kye-Hyun Kyung; Jeong-Hyuk Choi
Most memory-chip manufacturers keep trying to supply cost-effective storage devices with high-performance characteristics such as shorter tPROG, lower power consumption and higher endurance. For many years, every effort has been made to shrink die size to lower cost and to improve performance. However, the previously used node-shrinking methodology is facing challenges due to increased cell-to-cell interference and patterning difficulties caused by decreasing dimension. To overcome these limitations, 3D-stacking technology has been developed. As a result of long and focused research in 3D stacking technology, we succeed in developing 128 Gb 3b/cell Vertical NAND with 32 stack WL layers for the first time, which is the smallest 128 Gb NAND Flash. The die size is 68.9 mm 2, program time is 700 us and I/O rate is 1 Gb/s.
international solid-state circuits conference | 2015
Jaewoo Im; Woopyo Jeong; Doohyun Kim; Sang-Wan Nam; Dongkyo Shim; Myung-Hoon Choi; Hyun-Jun Yoon; Dae-Han Kim; Y. Kim; Hyun Wook Park; Donghun Kwak; Sang-Won Park; Seok-Min Yoon; Wook-ghee Hahn; Jinho Ryu; Sang-Won Shim; Kyung-Tae Kang; Sung-Ho Choi; Jeong-Don Ihm; Young-Sun Min; In-Mo Kim; Doo-Sub Lee; Ji-Ho Cho; Oh-Suk Kwon; Ji-Sang Lee; Moosung Kim; Sang-Hyun Joo; Jae-Hoon Jang; Sang-Won Hwang; Dae-Seok Byeon
Most memory-chip manufacturers keep trying to supply cost-effective storage devices with high-performance characteristics such as smaller tPROG, lower power consumption and longer endurance. For many years, every effort has been made to shrink die size to lower cost and to improve performance. However, the previously used node-shrinking methodology is facing challenges due to increased cell-to-cell interference and patterning difficulties caused by decreasing dimension. To overcome these limitations, 3D-stacking technology has been developed. As a result of long and focused research in 3D stacking technology, 128Gb 2b/cell device with 24 stack WL layers was announced in 2014 [1].
Archive | 2006
Sang-Won Hwang; Dong-Kyu Youn
Archive | 2011
Sang-Won Hwang; Chan-Ho Kim
Archive | 2008
Jin-Yub Lee; Sang-Won Hwang
Archive | 2006
Sang-Won Hwang; Jong-Soo Lee
Archive | 2003
Sang-Won Hwang; Sung-Soo Lee
Archive | 2004
Sang-Won Hwang; Jin-Yub Lee; Bum-soo Kim; Kwang-yoon Lee; Chanik Park
Archive | 2007
Sang-Won Hwang; Jong-Soo Lee
Archive | 2010
Sang-Won Hwang