Sangdo Park

Die matching algorithm for enhancing parametric yield of 3D ICs

This paper addresses the problem of selecting (i.e., matching) dies to be bonded together in 3D IC design to improve parametric yield, producing 3D chips that are highly tolerant to the on-package induced timing variation. For two-layered 3D ICs, the corresponding two-dimensional die-to-die matching problem can be formulated into the maximum bipartite matching problem which is solvable optimally in polynomial time. However, for 3D ICs with K(>; 2) layers, the corresponding K-dimensional die-to-die matching problem is known intractable. The previous approach applies the optimal two-dimensional matching algorithm repeatedly to find a solution of the K-dimensional die matching problem. The inherent limitation of the previous approach is that each of the optimal two-dimensional matchings applied in the iteration process is completely isolated and localized, resulting in globally unoptimized K-dimensional matching solutions. This work overcomes this limitation. Precisely, we propose a new enhanced two-dimensional die matching formulation based on finding a maximum flow of minimum cost in a network, which can be solved optimally in polynomial time while facilitating finding globally improved K-dimensional matching solutions when it is iteratively applied. From experimental results with benchmark circuits, we confirm that our proposed algorithm is able to find solutions that produce 5%, 8%, and 12% improved parametric yield for 3-layered, 4-layered, and 5-layered 3D ICs compared to the results of previous work, respectively.

Inferring contexts of driving modes for better user experience of mobile service

Operating a Smartphone to use a mobile service while driving can be dangerous by distracting users from driving. Recognizing users context of driving and automatically activating a corresponding mobile service can be a possible way to reduce users manual operations and provide a better driving experience with Smartphone in a safe way while driving. In this paper we present an efficient method for recognizing user contexts of driving based on accelerometer signals of Smartphone. Our method uses well-designed features that are not only effective to discriminate driving contexts but also efficient to compute on a Smartphone device in real-time. Throughout real-world data set, we also demonstrate some of useful behaviors of our proposed method.

Data-driven state-of-health estimation of EV batteries using fatigue features

Estimating State-of-Health(SOH) for electric vehicle(EV) batteries is the most crucial to determine replacement time of the battery or to calculate driving mileage. However, partial charge and discharge, or steep changes of current loads imposed in EV increase estimation error. In this paper, we present a data-driven method for Battery Management System(BMS) to precisely estimate the SOH reflecting batterys stress pattern.

Post-silicon tuning aware wafer matching algorithm for 3d integration of ICs

This work addresses the problem of wafer-to-wafer matching algorithm for 3D integration of ICs. One critical limitation of the traditional wafer matching methods is that they have attempted to maximize the number of resulting 3D ICs with no faulty (bad) die, but never took into account the time variation between the individual dies in a 3D integrated chip. We show that without considering time variation between dies as well as within wafers during wafer-to-wafer matching, a more aggressive post-silicon tuning is required with increased design cost or a reduced parametric yield of chips is resulted. To overcome this limitation, we propose a post-silicon tuning aware comprehensive wafer matching algorithm to improve the parametric yield of 3D chips. Through experiments with benchmark designs, it is shown that the proposed wafer matching algorithm is able to enhance the parametric yield by up to 8%.

Allocation and optimization of Post-silicon tunable buffers in TSV based heterogeneous 3D ICs

Through-silicon via (TSV) based 3D IC design is a promising solution to reducing the length of interconnects and improving the power and speed. However, when heterogeneous dies are stacked together to form a 3D IC, a considerable timing discrepancy among the layers could happen since the devices in different layers might have been affected quite differently by process variations. With this respect, this work makes two contributions: (1) proposing a PST buffer allocation scheme in 3D ICs to resolve the timing discrepancy between dies; (2) with the proposed allocation scheme, proposing a technique that is able to minimize the total cost of PST buffer implementation.

Edge layer embedding algorithm for mitigating on-package variation in 3D clock tree synthesis

Abstract A 3D stacked IC is made of multiple dies possibly with heterogeneous process technologies. Therefore, the die-to-die variation between the stacked dies creates on-package variation in a 3D chip. In this paper, we analyze the effect of on-package variation on the 3D clock trees and address the problem of on-package variation aware layer embedding in 3D clock tree synthesis. The layer embedding problem is divided into two sub-problems: clock node embedding and clock edge embedding. While the clock node embedded problem has been intensively investigated by the previous 3D clock tree synthesis flows because the solution directly determines the TSV allocation, the clock edge embedding problem has not been fully addressed yet. We show in this work that a careful clock edge embedding can greatly reduce the impact of on-package variation on the 3D clock skew , thereby enhancing chip yield, and propose a two-step solution to the problem of on-package variation aware layer embedding of clock edges. Specifically, we formulate the edge embedding problem into a problem of maximizing the sharing of layers among the clock paths to minimize the impact of on-package variation globally and solve it efficiently, followed by applying a fine-grained refinement technique to balance the clock latency locally among the clock paths. From the experiments with Benchmark circuits, we confirm that compared to the results produced by the conventional on-package variation unaware layer embedding of clock edges, the proposed algorithm is able to improve the chip yield by 6.2–25.8% and 5.3–44.4% for 2-layered and 4-layered 3D designs, respectively.

Sound-based real-time context recognition on smartphone

Recently, many people bring their smartphone almost all the time, so the smartphone is considered as a proper device for context recognition. However, the computing power of smartphone is relatively limited to analyze rich contextual cues. In this paper, we present a simple method for smartphone to recognize the context based on sound signals.

A context aware engine for multimedia applications on smartphone

High complexity of understanding users current situation is a crucial barrier to popularize context aware applications on smartphone. In order to overcome this barrier, we propose a context aware engine which eases the development of intelligent applications. Key feature of the engine is dynamic reconfiguration of the knowledge base depending on the current environments using linked data. We validated the usefulness of this feature via two in-house applications.

A Re-configurable Context-Aware Engine for Mobile Devices

Despite the increasing request for intelligent applications with the heavy use of smart phone, little of them are available in daily life. One reason must be the high complexity of understanding users situation. For application (app) developers, knowing users context usually takes much more time and efforts than taking some useful actions. To help developing intelligent apps, we have proposed a mobile context-aware engine called Intelligent Mobile Platform (IMP). It provides users current context to apps as a background service in android mobile phones. Especially, depending on users current environments such as location, active apps, etc., IMP dynamically extends or shrinks its knowledge base. We believe that this dynamic reconfiguration is essential for mobile environment where user continuously changes his/her location and contexts. In this paper, we describe the reconfiguration part in detail. This feature is tested by three in-house apps with the IMP prototype on SAMSUNG Galaxy S II phone.

Clock design techniques considering circuit reliability

This paper overviews clock design problems related to the circuit reliability in deep submicron design technology. The topics include clock polarity assignment problem for reducing peak power/ground noise, clock mesh network design problem for tolerating clock delay variation, electromagnetic interference (EMI) aware clock optimization problem, adjustable delay buffer (ADB) allocation and assignment problem to support multiple voltage mode designs, and state encoding problem for reducing peak current in sequential elements. The last topic belongs to FSM design and is not directly related to the clock design, but it can be viewed that reducing noise at the sequential elements driven by clock signal is contained in the spectrum of reliable circuit design from clock source down to sequential elements inclusive.