Taewhan Kim

DC–DC Converter-Aware Power Management for Low-Power Embedded Systems

Most digital systems are equipped with dc-dc converters to supply various levels of voltages from batteries to logic devices. DC-DC converters maintain legal voltage ranges regardless of the load current variation as well as battery voltage drop. Although the efficiency of dc-dc converters is changed by the output voltage level and the load current, most existing power management techniques simply ignore the efficiency variation of dc-dc converters. However, without a careful consideration of the efficiency variation of dc-dc converters, finding a true optimal power management will be impossible. In this paper, we solve the problem of energy minimization with the consideration of the characteristics of power consumption of dc-dc converters. Specifically, the contributions of our work are as follows: 1) We analyze the effects of the efficiency variation of dc-dc converters on a single-task execution in dynamic voltage scaling (DVS) scheme and propose the technique for dc-dc converter-aware energy-minimal DVS. 2) is then extended to embed an awareness of the characteristics of dc-dc converters in general DVS techniques for multiple tasks. 3) We go on to propose a technique called for generating a dc-dc converter that is most energy efficient for a particular application. 4) We also present an integrated framework, i.e., , based on and , which addresses dc-dc converter configuration and DVS simultaneously. Experimental results show that is able to save up to 24.8% of energy compared with previous power management schemes, which do not consider the efficiency variation of dc-dc converters.

Optimal voltage allocation techniques for dynamically variable voltage processors

This paper presents a set of new important results for the problem of task scheduling and voltage allocation in dynamically variable voltage processor for minimizing the total processor energy consumption. The contributions are two folds: (1) For given multiple discrete supply voltages and tasks with arbitrary arrival-time/deadline constraints, we propose a voltage allocation technique which produces a feasible task schedule with optimal processor energy consumption; (2) We then extend the problem to include the case in which tasks have non-uniform load (i.e., switched) capacitances, and solve it optimally.

Circuit optimization using carry-save-adder cells

Carry-save-adder (CSA) is the most often used type of operation in implementing a fast computation of arithmetics of register-transfer-level design in industry. This paper establishes a relationship between the properties of arithmetic computations and several optimizing transformations using CSAs to derive consistently better qualities of results than those of manual implementations. In particular, we introduce two important concepts, operation duplication and operation split, which are the main driving techniques of our algorithm for achieving an extensive utilization of CSAs. Experimental results from a set of typical arithmetic computations found in industry designs indicate that automating CSA optimization with our algorithm produces designs with up to 53% faster timing and up to 42% smaller area.

Memory access scheduling and binding considering energy minimization in multi-bank memory systems

Memory-related activity is one of the major sources of energy consumption in embedded systems. Many types of memories used in embedded systems allow multiple operating modes (e.g., active, standby, nap, power-down) to facilitate energy saving. Furthermore, it has been known that the potential energy saving increases when the embedded systems use multiple memory banks in which their dperating modes are controlled independently. In this paper, we propose (a compiler-directed) integrated approach to the problem of maximally utilizing the operating modes of multiple memory banks by solving the three important tasks simultaneously: (I) assignment of variables to memory banks, (2) scheduling of memory aicess operations, and (3) defemination of operating modes o/banks. Specifically, for an instance of tasks 1 and 2, we formulate task 3 as a shortest path(SP) problem in a network and solved it optimally. We then develop an SP-based heuristic that solves tasks 2 and 3 efficiently in an integrated fashion. We then extend the proposed approach to address the limited register constraint in processor. Fmm experiments with a set of benchmark programs, we confirm that the proposed approach is able to reduce the energy consumption by 15.76% over that by the conventional greedy approach.

Clock tree embedding for 3D ICs

This paper addresses a fundamental problem of zero skew clock tree embedding problem in 3D ICs. We propose an algorithm, called ZCTE-3D, for solving the zero skew clock tree embedding problem in 3D ICs for a given tree topology. The primary objective is to minimize the cost of TSVs together with finding embedding layers and the secondary objective is to minimize the cost of wirelength. We show that ZCTE-3D solves the problem optimally in polynomial time under the linear delay model, while it solves the problem suboptimally under the Elmore delay model. We also propose an effective 3D clock tree synthesis flow by integrating a multi-layer tree topology generation algorithm, called MMM-3D, into ZCTE-3D. Through an extensive exploitation of ZCTE-3D in experiments, we have analyzed the relation between the number of TSVs, the total wirelength, and tree topology. When compared with the results produced by the previous 3D clock tree synthesis algorithm BURITO, experimental results show that ZCTE-3D uses on average 10% less number of TSVs with similar wirelength and delay for the same tree topologies. Furthermore, by generating tree topologies with MMM-3D, we are able to reduce the number of TSVs by 10% on average even with 4% shorter wirelength and 2% reduced delay.

Utilization of Multiport Memories in Data Path Synthesis

In this paper, a new approach to the problem of allocating multiport memory modules for data storage is presented. Previous approaches divide the allocation problem into two separate steps: (i) grouping the variables (or registers) to form memory modules and (ii) determining the interconnections between the memory modules and functional units. Yet, there is no easy way to predict the result of step (ii) during step (i). In our approach, we place primary importance on the cost of interconnections. Consequently, we try to minimize the cost of interconnections first and then to group the variables to form memory modules later. For a number of benchmark problems, it has been shown that this approach is quite effective.

Arithmetic optimization using carry-save-adders

Carry-save-adder(CSA) is the most often used type of operation in implementing a fast computation of arithmetics of register-transfer level design in industry. This paper establishes a relationship between the properties of arithmetic computations and several optimizing transformations using CSAs to derive consistently better qualities of results than those of manual implementations. In particular, we introduce two important concepts, operation-duplication and operation-split, which are the main driving techniques of our algorithm for achieving an extensive utilization of CSAs. Experimental results from a set of typical arithmetic computations found in industry designs indicate that automating CSA optimization with our algorithm produces designs with significantly faster timing and less area.

High-level synthesis for low power based on network flow method

We propose an effective algorithm for power optimization in behavioral synthesis. In previous work, it has been shown that several hardware allocation/binding problems for power optimization can be formulated as network flow problems and cand be solved optimally. However, in these formulations, a fixed schedule was assumed. In such a context, one key problem is that given an optimal network flow solution to a hardware allocation/binding problem for a given schedule, how to generate a new optimal network-flow solution rapidly for a local change of the given schedule. To this end, from a comprehensive analysis of the relation between network structure and flow computation, we devise a two-step procedure: Step 1) a max-flow computation step which finds a valid (maximum) flow solution while retaining the previous (maximum flow of minimum cost) solution as much as possible and Step 2) a min-cost computation step which incrementally refines the flow solution obtained in Step 1, using the concept of finding a negative cost cycle in the residual graph for the flow. The proposed algorithm can be applied effectively to several important high-level optimization problems (e.g., allocations/bindings of functional units, registers, buses, and memory ports) when we have the freedom to choose a schedule that will minimize power consumption. Experimental results (for bus synthesis) on benchmark problems show that our designs are 4%-40% more power-efficient over the designs produced by a random-move based solution and a clock-step based optimal solution, which is due to a) exploitation of the effect of scheduling and b) optimal binding for every schedule instance. Furthermore, our algorithm is about 2.6 times faster in run time over the full network flow based (optimal) algorithm, which is due to c) our novel (two-step) mechanism which utilizes the previous flow solution to reduce redundant flow computations.

Clock tree synthesis with pre-bond testability for 3D stacked IC designs

This paper proposes comprehensive solutions to the clock tree synthesis problem that provides pre-bond testability for 3D IC designs. In 3D ICs, it is essential to stack only good dies by testing the individual dies before stacking. For the clock signaling, the pre-bond testing requires a complete 2D clock tree on each die. The previous work enables the pre-bond testability by allocating specially designed resources called TSV-buffers and redundant trees with transmission gates. We proposes viable solutions to the two fundamental problems of the previous work: (1) using much less buffer resources by preventing (potentially ‘bad’) TSV-buffers with a new tree topology generation algorithm; (2) completely removing the transmission gate control lines by using a specially designed component called self controlled clock transmission gate (SCCTG). Compared to the existing 3D tree topology generation algorithms, solution 1 can use 56%–88% less number of TSVs, 53%–67% less number of buffers, 22%–65% less total wirelength, and 26%–43% less clock power for the benchmark circuits with dense sink placements. Moreover, solution 2 reduces the total wirelength of all the benchmark circuits by 17% and 23% on average for the 2-die and 4-die stacked 3D ICs, respectively.

Low power bus encoding with crosstalk delay elimination [SoC]

In deep-submicron (DSM) technology, minimizing the propagation delay and power consumption on buses are two of the most important design objectives in system-on-chip (SoC) design. In particular, coupling effects between wires on the bus cause serious problems such as crosstalk delay, noise, and power consumption. Most of the previous works on bus encoding are targeted either (1) to minimize the power consumption on the bus or (2) to minimize the crosstalk delay, but not both. In this paper, we propose a new bus encoding algorithm which not only minimizes the dynamic power consumption on the bus but also eliminates the crosstalk delay. We achieve the combined objective of (1) and (2) by analyzing, formulating and solving the problem of minimizing a weighted sum of the self transition and cross-coupled transition activities on bus in the context of the concept of self-shield encoding (whose fundamental theory is well studied recently by B. Victor and K. Keutzer (Proc. ICCAD, 2001)). From experiments using a set of benchmark designs, it is shown that the proposed encoding technique consumes 15.4%-47.4% less power over the existing techniques, while totally eliminating the crosstalk delays.