Sanggyu Park

Reusable component IP design using refinement-based design environment

We propose a method of enhancing the reusability of the component IPs by separating communication and computation for a system function. In this approach, we assume that the component designers describe mainly the computation part of the component, and the system designer can construct the communication part by using our refinement-based design environment. Moreover, we introduced a concept of the communication architecture template tree (CATree), which helps IP designers to effectively separate computation and communication for a system function. We confirmed that this approach is effective by applying it to a H.264 decoder design

A C/C++-based functional verification framework using the SystemC verification library

This paper describes SoCBase-VL, which is a C/C++ based integrated framework for SoC functional verification. It has a layered architecture which provides easier test-bench description, automatic verification of bus interfaces and seamless testbench migration. This framework does not require verification engineers to learn other verification languages as long as they have sufficient knowledge on both C/C++ and SystemC. We have confirmed its usefulness by applying it to a TFT-LCD controller verification.

A Mixed-Level Virtual Prototyping Environment for Refinement-Based Design Environment

The communication architecture template tree (CAT-tree) is an abstraction of the specific range of communication functions and architectures, which can facilitate system function capture and communication architecture refinement. In this paper, we explain a TLM-RTL-SW mixed-level simulation environment that is useful for the functional verification of partially refined system models. We employed SystemC, GNU Gdb and a HDL simulator for the simulation of CATtree-based TLM, SW and HW, respectively. We also employed a new operating system, DEOS so that each SystemC-based TLMs can be cross-compiled to be executed as software models on the target processors. We evaluated the flexibility and simulation performance of the virtual simulation environment with an H.264 decoder design example

A mixed-level virtual prototyping environment for SystemC-based design methodology

We propose a flexible mixed-level virtual prototyping environment, where models in different abstraction levels such as transaction level, register-transfer level, and software level can be co-simulated together. In the proposed environment, the designers should capture a transaction level system model before hardware-software partitioning, from which mixed-level virtual prototyping models can be refined with pre-defined and pre-verified communication primitives. We explain several techniques employed in the environment such as ID ports for software template efficiency, abstraction adapters in SystemC for mixed level simulation, and trace-driven simulation for faster performance evaluation. Moreover, transaction level descriptions in SystemC can be compiled and executed as software together with the DEOS, which is an operating system that provides SystemC APIs. We compared the simulation speed of several mixed-level virtual prototypes of a H.264 decoder to show the effectiveness of the proposed environment.

A two-week program for a platform-based SoC design

This paper describes a two-week program for a platform-based SoC design using SoCBase 1.0, a platform developed in the Center for SoC Design Technology. This program consists of 4 lectures and 9 laboratories. It covers several design steps from the transaction level to the FPGA prototype level for a Motion JPEG decoder. In this program we employed an SoC design flow based on SoCBase 1.0. It is targeted for graduate students and ASIC designers out in the industry. More than 100 engineers and graduate students have completed this program in 2004.

Implementation of a H.264 decoder with Template-based Communication Refinement

We described an H.264 decoder implemented with our design methodology, in which a system function model of transaction level is first captured in SystemC and refined into RTL with a library of communication templates. We determined its communication architecture by exploring the design space with template-based communication refinement to meet its requirement of decoding VGA 30 frames per second at a clock frequency of 50MHz