Sangyong Yoon | Researchain

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Featured researches published by Sangyong Yoon.

international solid-state circuits conference | 2012

A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology

Dae-Yeal Lee; Ik Joon Chang; Sangyong Yoon; Joon-Suc Jang; Dong-Su Jang; Wook-ghee Hahn; Jong-Yeol Park; Doo-gon Kim; Chi-Weon Yoon; Bong-Soon Lim; Byung-Jun Min; Sung-Won Yun; Ji-Sang Lee; Il-Han Park; K. Kim; Jeong-Yun Yun; Y. Kim; Yongsung Cho; Kyung-Min Kang; Sang-Hyun Joo; Jin-Young Chun; Jung-No Im; Seunghyuk Kwon; Seokjun Ham; An-Soo Park; Jae-Duk Yu; Nam-Hee Lee; Taesung Lee; Moosung Kim; Hoo-Sung Kim

The market growth of mobile applications such as smart phones and tablet computers has fueled the explosive demand of NAND Flash memories having high density and fast throughput. To meet such a demand, we present a 64Gb multilevel cell (MLC) NAND Flash memory having 533Mb/s DDR interface in sub-20nm technology. Large floating-gate (FG) coupling interference and program disturbance are major challenges to impede the scaling of NAND Flash memories in sub-20nm technology node [1]. In this paper, we present correction-before-coupling (CBC) reprogram and P3-pattern pre-pulse scheme, allowing us to overcome large FG coupling interferences. We improve program disturbance by inventing inhibit-channel-coupling-reduction (ICCR) technique. In addition, we achieve a 533Mb/s DDR interface by employing a wave-pipeline architecture [2].

symposium on vlsi circuits | 2012

A new 3-bit programming algorithm using SLC-to-TLC migration for 8MB/s high performance TLC NAND flash memory

Seung-Hwan Shin; Dongkyo Shim; Jaeyong Jeong; Oh-Suk Kwon; Sangyong Yoon; Myung-Hoon Choi; Tae-Young Kim; Hyun Wook Park; Hyun-Jun Yoon; Youngsun Song; Yoon-Hee Choi; Sang-Won Shim; Yang-Lo Ahn; Kitae Park; Jinman Han; Kye-Hyun Kyung; Young-Hyun Jun

We have developed a new 3-bit programming algorithm of high performance TLC(Triple-level-cell, 3-bit/cell) NAND flash memories for 20nm node and beyond. By using the proposed 3-bit algorithm based on reprogramming with SLC-to-TLC migration, performance and BER is improved by 50% and 68%, respectively, compared to conventional method. The proposed algorithm is successfully implemented in 21nm 64Gb TLC NAND flash product that provides 8MB/s write and 400MB/s read throughputs.

international solid-state circuits conference | 2011

A 7MB/s 64Gb 3-bit/cell DDR NAND flash memory in 20nm-node technology

Kitae Park; Oh-Suk Kwon; Sangyong Yoon; Myung-Hoon Choi; In-Mo Kim; Bo-Geun Kim; Minseok S. Kim; Yoon-Hee Choi; Seung-Hwan Shin; Youngson Song; Joo-Yong Park; Jae-Eun Lee; Changgyu Eun; Ho-Chul Lee; Hyeong-Jun Kim; J.Y. Lee; Jong-Young Kim; Tae-Min Kweon; Hyun-Jun Yoon; Tae-hyun Kim; Dongkyo Shim; Jong-Sun Sel; Ji-Yeon Shin; Pan-Suk Kwak; Jinman Han; Keon-Soo Kim; Sung-Soo Lee; Young-Ho Lim; Tae-Sung Jung

Recently, the demand for 3b/cell NAND flash has been increasing due to a strong market shift from 2b/cell to 3b/cell in NAND flash applications, such as USB disk drives, memory cards, MP3 players and digital still cameras that require cost-effective flash memory. To further expand the 3b/cell market, high write and read performances are essential [1]. Moreover, the device reliability requirements for these applications is a challenge due to continuing NAND scaling to sub-30nm pitches that increases cell-to-cell interference and disturbance. We present a high reliability 64Gb 3b/cell NAND flash with 7MB/s write rate and 200Mb/s asynchronous DDR interface in a 20m-node technology that helps to meet the expanding market demand and application requirement.

Archive | 2011