Sangho Shin

Memristor Applications for Programmable Analog ICs

This paper demonstrates that memristors can be used to implement programmable analog circuits, leveraging memristors fine-resolution programmable resistance without causing perturbations due to parasitic components. Fine-resolution programmable resistance is achieved by varying the amount of flux across memristors. The resistance programming can be achieved by controlling the input pulsewidth and its frequency. For demonstration, a memristor is designed for a pulse-programmable midband differential gain amplifier with fine resolution.

Compact Models for Memristors Based on Charge-Flux Constitutive Relationships

This paper introduces compact models for memristors. The models are developed based on the fundamental constitutive relationships between charge and flux of memristors. The modeling process, with a few simple steps, is introduced. For memristors with limited resistance ranges, a simple method to find their constitutive relationships is discussed, and examples of compact models are shown for both current-controlled and voltage-controlled memristors. Our models satisfy all of the memristor properties such as frequency dependent hysteresis behaviors and also unique boundary assurance to simulate memristors whether they behave memristively or resistively. Our models are implementable in circuit simulators, including SPICE, Verilog-A, and Spectre.

Reconfigurable Stateful nor Gate for Large-Scale Logic-Array Integrations

This brief presents a stateful logic gate based on memristive devices that functions as high-fan-in NOR gates. The proposed logic structure executes multiple implications concurrently in a single step and thus enables fast logic operations reducing the number of pipeline steps. By mapping the logic units to the field-programmable nanowire interconnect fabric, a reconfigurable 2-D logic array for general-purpose functions can be implemented by configuring nanowire crossbar switches.

Memristor-based fine resolution programmable resistance and its applications

This paper demonstrates that memristors can be used to form a fine resolution programmable resistance without perturbations by parasitic components. By exploiting the memristor characteristics, fine resolution programmable memristance is achieved by varying the amount of charges flowing or flux across the memristor. Under the same circuit configuration with same or even less amount of parasitics, memristance is reconfigured with fine resolution by controlling the input pulse width and its frequency. This paper shows an example of pulse programmed memristors and their analog circuit applications.

Field Programmable Stateful Logic Array

Recently, researchers have demonstrated that memristive switches can be used to implement logic and latches as well as memory and programmable interconnects. In this paper, we propose a novel stateful logic pipeline architecture based on memristive switches. The proposed architecture mapped to the field programmable nanowire interconnect fabric produces a field programmable stateful logic array, in which general-purpose computation functions can be implemented by configuring only nonvolatile nanowire crossbar switches. CMOS control switches are used to isolate stateful logic units so that multiple operations can be executed in parallel. Since basic operation of the stateful logic, namely, material implication, cannot fan out, a new basic AND operation which can duplicate output is proposed. The basic unit of the proposed architecture is designed to execute multiple basic operations concurrently in a step so that each basic unit implements a large fan-in OR or NOR gate. The fine-grain ultradeep constant-throughput pipeline properties pose new design automation problems. We address some of the issues, in particular logic representation using OR-inverter graphs, two-level optimization synthesis strategy, data synchronization with data forwarding, stall-free pipelined finite state machines, and constraints for synthesis and mapping onto the fabric.

Analysis of Passive Memristive Devices Array: Data-Dependent Statistical Model and Self-Adaptable Sense Resistance for RRAMs

In this paper, a 2 × 2 equivalent statistical circuit model is presented to deal with sneak currents and random data distributions for design and analysis of n x m passive memory arrays of memristive devices. This data-dependent 2 × 2 model enables a broad range of analysis, such as the optimum detection voltage margin, with computational efficiency and no limit on the memory array size. We propose self-adaptable sense resistors that can find their statistical optimum values for reading stored data patterns by composing them with either a replica of a part of resistive random access memory (RRAM) array or a part of RRAM array itself. Self-adaptable resistors can increase the average voltage detection margin by 46%, and reduce the average current consumption by 14% for the case of a 128 × 128 passive array with OFF-to-ON resistance ratio of 103.

4.2W CMOS Frequency Synthesizer for 2.4GHz ZigBee Application with Fast Settling Time Performance

A new frequency synthesizer with low-power and short settling time is introduced. With two-point channel controls for an integer-N PLL, we have achieved a near zero settling time for any frequency change in 2.4GHz ZigBee band. By utilizing a vertical-NPN parasitic transistor for the VCO biasing, the close-in phase noise has been improved by 5dB from the case of MOS biasing. A modified-TSPC topology is proposed for low-voltage frequency divider circuits. Using the 1.2V supply voltage for 0.18mum CMOS, the power consumption is only 4.2mW and the phase noise is -116.5dBc/Hz at 1MHz offset

Stateful logic pipeline architecture

Recently, researchers have demonstrated that memristive switches can be used to implement logic and latches as well as memory and programmable interconnects. In this paper, we propose a novel stateful logic pipeline architecture based on memristive switches. CMOS control switches are used to isolate stateful logic units so that multiple operations can be executed in parallel. Since basic operation of the stateful logic, namely material implication, cannot fan out, a new AND basic operation which can duplicate output is proposed. The basic unit of the proposed architecture is designed to execute multiple basic operations concurrently in a step so that each basic unit implements a large fan-in OR or NOR gate. Due to the fine-grain ultra-deep constant-throughput pipeline properties, design paradigm shifts are required. We address some of the issues, in particular logic representation using Staged OR-NOR Graphs (SONGs), and data synchronization with data forwarding.

Fast- Frequency Offset Cancellation Loop Using Low-IF Receiver and Fractional-N PLL

This brief introduces a simple circuit solution to secure loop stability of an analog-domain fast-frequency offset cancellation loop (OCL). The OCL is composed of a low-IF receiver, phase-domain frequency offset detector (OD), and fractional-N phase-locked loop (PLL). Since the OCL uses a phase-domain OD, a stability concern is essentially needed for its practical use. From the frequency-domain analysis, a PLL bandwidth adaptation by controlling charge-pump currents is proposed to achieve a strong stability with phase-margin of more than 60deg. Additionally, a tradeoff between the OCL accuracy and hardware complexity is discussed, and a design example is shown for the 2.4-GHz ZigBee application. With 4-MHz IF, designed for an 0.18-mum CMOS process, our circuit takes 30 mus to reject the frequency offset of +200 kHz within the accuracy of plusmn5 ppm, with 60-DFFs for a time-to-digital converter

Experimental validation of the power blurring method

Accurate estimation of temperature profiles from the underlying power dissipation profiles has become an important tool for chip designers and reliability engineers due to increasing power dissipation in ICs and associated thermal effects. ICs surface temperature is conventionally calculated by finite element or finite difference solvers. These methods yield accurate results but the computation time could be several hours to obtain accurate dynamic temperature profiles with high spatial resolution. Previously, we have developed an ultra fast IC temperature profile calculation technique, named as Power Blurring (PB), which dramatically reduces the computation time by a factor of more than a thousand and keeps the error within 5% comparing to finite element analysis done by ANSYS. In this paper, the power blurring method is validated against experimental measurements using a thermal test chip which was designed based on 5-stage ring oscillators. The simulation results and the measurement data show good agreements.