Sanghyeon Baeg

SRAM Interleaving Distance Selection With a Soft Error Failure Model

The significance of multiple cell upsets (MCUs) is revealed by sharing the soft-error test results in three major technologies, 90 nm, 65 nm, and 45 nm. The effectiveness of single-bit error correction (SEC) codes can be maximized in mitigating MCU errors when used together with the interleaving structure in memory designs. The model proposed in this paper provides failure probability to probabilistically demonstrate the benefits of various interleaving scheme selections for the memories with SEC. Grouped events such as MCU are taken into account in the proposed model by using the compound Poisson process. As a result of the proposed model, designers can perform predictive analysis of their design choices of interleaving schemes. The model successfully showed the difference in failure probability for different choices of interleaving schemes. The model behaved as the upper bound for failure probability when compared to the neutron test data with the 45-nm static-random-access memory (SRAM) design.

Low-Power Ternary Content-Addressable Memory Design Using a Segmented Match Line

Power consumption in match lines is the most critical issue for low-power ternary content-addressable memory (TCAM) designs. In the proposed match-line architecture, the match line in each TCAM word is partitioned into four segments and is selectively pre-charged to reduce the match-line power consumption. The partially charged match lines are evaluated to determine the final comparison result by sharing the charges deposited in various parts of the partitioned segments. This arrangement reduces the match-line power consumption by reducing effective capacitor loading and voltage swing at match lines. The segmented architecture also enhances operational speed by evaluating multiple segments in parallel and by overlapping the pre-charging and evaluation stages. 512 times 72 TCAM is designed using 0.18-mum CMOS technology. The extracted RC values are used to show the power reduction benefits. The sample design demonstrated that the match-line power consumption using a segmented match line was conservatively 44% of that produced by traditional parallel TCAM. The power savings by segmenting match lines can be up to 41% over a low-voltage swing technique due to the independent discharge capability in segmented match-line architecture.

Minimizing Soft Errors in TCAM Devices: A Probabilistic Approach to Determining Scrubbing Intervals

Ternary content addressable memory (TCAM) is more susceptible to soft errors than static random access memory (SRAM). The large di/dt issue during comparison operation reduces operating voltage ranges, which in turn reduces soft error immunity. The tight structural coupling of TCAM comparison circuits and memory cells does not allow for an interleaving design scheme in mitigating soft errors. Regular scrubbing of stored content can greatly mitigate the reliability issue caused by soft errors. However, frequent scrubbing can also affect device performance. The scrubbing interval should be determined to facilitate both reliability and performance. This paper proposes a novel, model-based approach that includes both single-bit upsets (SBUs) and multi-cell upsets (MCUs) to determine the scrubbing interval by predictive and probabilistic failure rate analysis. This model uses the compound Poisson (CP) process to count clustered random events, which are common phenomena of soft errors in technologies that use chips under 90 nm. The 20 M TCAM with 90-nm CMOS technology was tested with 180-MeV neutron strikes. The scrubbing interval determined based on the proposed model is applied to the TCAM test results. The failure probabilities based on the CP model showed 31% overestimation on average compared to the same from the test data. Such overestimation is mainly due to the independent upset assumption in the proposed model and can enable use of the model as worst case analysis. The worst case comparison with the test data showed 1.7% overestimation, which can tell the proposed model is effective in predicting upper-bound soft error reliability.

Protection of Memories Suffering MCUs Through the Selection of the Optimal Interleaving Distance

Interleaving, together with single error correction codes (SEC), are common techniques to protect memories against multiple cell upsets (MCUs). This kind of errors is increasingly important as technology scales, becoming a prominent effect, and therefore greatly affecting the reliability of memories. Ideally, the interleaving distance (ID) should be chosen as the maximum expected MCU size. In this way, all errors in an MCU would occur in different logical words, thus being correctable by the SEC codes. However, the use of large interleaving distances usually results in an area increase and a more complex design of memories. In this paper, the selection of the optimal interleaving distance is explored, keeping the area overhead and complexity as low as possible, without compromising memory reliability.

Hybrid Partitioned SRAM-Based Ternary Content Addressable Memory

Although content addressable memory (CAM) provides fast search operation; however, CAM has disadvantages like low bit density and high cost per bit. This paper presents a novel memory architecture called hybrid partitioned static random access memory-based ternary content addressable memory (HP SRAM-based TCAM), which emulates TCAM functionality with conventional SRAM, thereby eliminating the inherited disadvantages of conventional TCAMs. HP SRAM-based TCAM logically dissects conventional TCAM table in a hybrid way (column-wise and row-wise) into TCAM sub-tables, which are then processed to be mapped to their corresponding SRAM memory units. Search operation in HP SRAM-based TCAM involves two SRAM accesses followed by a logical ANDing operation. To validate and justify our approach, 512 × 36 HP SRAM-based TCAM has been implemented in Xilinx Virtex-5 field programmable gate array (FPGA) and designed using 65-nm CMOS technology. Implementation in FPGA is advantageous and a beauty of our proposed TCAM because classical TCAMs cannot be implemented in FPGA. After a thorough analysis, we have concluded that energy/bit/search of the proposed TCAM is 85.72 fJ.

Optimizing Scrubbing Sequences for Advanced Computer Memories

Advanced memories are designed using smaller geometries and lower voltages. This enables larger levels of integration and reduced power consumption, but makes memories more prone to suffer multibit soft errors. In this scenario, scrubbing is a fundamental technique to avoid the accumulation of errors, which would lead to a failure of the system. Scrubbing is usually implemented in advanced memories. However, when the percentage of multibit soft errors is significant, the scrubbing sequence (the order in which the memory is scrubbed) becomes important for the reliability of the system. In this paper, a new procedure to perform scrubbing is presented, which offers a significant improvement in the reliability. In the presence of multiple cell upsets, the mean time to failure could be doubled with respect to the traditional approach.

An SEU-Tolerant DICE Latch Design With Feedback Transistors

This paper presents an SEU-tolerant Dual Interlocked Storage Cell (DICE) latch design with both PMOS and NMOS transistors in the feedback paths. The feedback transistors improve the SEU tolerance by increasing the feedback loop delay during the hold mode. The latch design was implemented in a shift register fashion at a 130-nm bulk CMOS process node. Exposures to heavy-ions exhibited a significantly higher upset LET threshold and lower cross-section compared with the traditional DICE latch design. Performance penalties in terms of write delay, power, and area are non-significant compared to traditional DICE design.

AC-JTAG: empowering JTAG beyond testing DC nets

Presents the new technology that extends todays JTAGs capability from DC domain to both AC and DC domains. New concept, AC_EXTEST is introduced to support AC interconnection test and to have backward compatibility with EXTEST. It leverages existing application software available within the boundary-scan test industry to promote this technology to the manufacturing floor with minimal impact.

Memory Reliability Model for Accumulated and Clustered Soft Errors

The soft error rates of memories are increased by high-energy particles as technology shrinks. Single-error correction codes (SEC), scrubbing techniques, and interleaving distance (ID) schemes are the most common approaches for protecting memories from soft errors. It is essential to employ analytical models to guide the selection of the interleaving distance; relying on rough estimates may lead to unreasonable design choices. The analytical model proposed in this paper includes the row clustering effects of the accumulated upsets, and was able to estimate the failure probability with a difference of only 0.015% compared to the test data for a 45 nm static random access memory (SRAM) design.

Active-precharge hammering on a row induced failure in DDR3 SDRAMs under 3× nm technology

This paper introduces the new failure mechanism manifested in DDR3 SDRAMs under 3× nm technology. The failure in normal cells is caused by iterative hammering accesses to a row within a refresh cycle. With the valid yet stressful access to a row, the charge in a DRAM cell leaked faster and the values of the stressed cells could not be retained. The three test parameters - tRP, data pattern, and temperature-were varied during the row hammering experiments to understand the contributions of each in triggering and accelerating the failing mechanisms. Here, we mainly discuss the experimental results of the commercial DDR3 components from three major memory vendors. All commercial DDR3 components failed much earlier than the specified limit of allowed accesses. For a vendor memory component, a cell started to fail after only 98K accesses to a row, which is about 7.54% of the specification-permitted accesses of 1,300K.