Soonyoung Lee

Study of Neutron Soft Error Rate (SER) Sensitivity: Investigation of Upset Mechanisms by Comparative Simulation of FinFET and Planar MOSFET SRAMs

The assessment of the soft-error rate (SER) of semiconductor devices continues to be important, even with the adoption of FinFET devices which overcome some important limitations of planar MOSFETs. The study in this paper presents both theoretical and experimental results via advanced simulation techniques, to investigate the difference between planar and FinFET devices in terms of SER. Neutron test results from different facilities are presented, and the observed differences in sensitivity are explained through theoretical analysis. In the second half of the paper, the test results are validated through TCAD and TFIT simulations using a calibrated technology response model. The analysis shows that the reduction in sensitivity of FinFET devices is primarily due to an increase in the threshold LET and a reduction in the sensitive volume due the shape of the transistor.

Radiation-induced soft error rate analyses for 14 nm FinFET SRAM devices

Radiation-induced Soft Error Rate (SER) of SRAM built in 14nm FinFET on bulk technology was extensively characterized. Two different SRAM cells, high-performance (HP) and high-density (HD), were irradiated with alpha particles, thermal neutrons, and high-energy neutrons. Empirical results reveal excellent SER performance of FinFET compared to the prior technology nodes, drastically reducing SER FIT rate by 5-10X. It is found that HP cell is more sensitive to a single event upset than HD cell design. We will discuss the effects of charge collection efficiency as one of major parameter and present supporting simulation results.

Memory Reliability Model for Accumulated and Clustered Soft Errors

The soft error rates of memories are increased by high-energy particles as technology shrinks. Single-error correction codes (SEC), scrubbing techniques, and interleaving distance (ID) schemes are the most common approaches for protecting memories from soft errors. It is essential to employ analytical models to guide the selection of the interleaving distance; relying on rough estimates may lead to unreasonable design choices. The analytical model proposed in this paper includes the row clustering effects of the accumulated upsets, and was able to estimate the failure probability with a difference of only 0.015% compared to the test data for a 45 nm static random access memory (SRAM) design.

Memory Reliability Analysis for Multiple Block Effect of Soft Errors

Multiple bit upsets (MBU) are analyzed from the perspective of the number of accessed blocks (NAB) in multiple memory block structures. The NAB represents the number of accessed blocks for a single memory operation. Statistical model of the MBU with regards to the NAB is developed, and its correlation to the test results presented. The tests were performed with neutron irradiation facility at The Svedberg Laboratory. The NAB in structure of multiple memory blocks is one of the most important parameter in determining the reliability of the memory. Although multiple cell upsets can be effectively spread out as multiple single bit upsets by interleaving distance scheme, the word failure rates are increased by combination of multiple events from multiple memory blocks. The proposed model can be effectively used for the estimation of the mean time to the failure with different design parameters during the early design states.

Soft Error Issues with Scaling Technologies

As transistor geometry shrinks, the erroneous and spurious charge from a particle strike tends to be shared by multiple nodes and causes multiple nodes upset. Such SEU mechanism invalidates the hardening principle of protecting a single node in relatively larger technologies. SEU needs to be accordingly understood and evaluated. In an 28-nm design example, SEU can happen in 6-day interval if no mitigation technique is used.

Reliability characterization of 10nm FinFET technology with multi-V T gate stack for low power and high performance

We report the reliability characterization of 10nm FinFET process technology. Unique reliability behavior by using multi-VTs through work function engineering is presented. Comparable intrinsic BTI, HCI and TDDB can be achievable vs. 14nm node, while transistors with different VT-types exhibit no extrinsic issues, can support different Vmax. Scaled taller and narrower fin shape increases the transistor self-heating which enhances PMOS HCI and on-state TDDB, yet can be mitigated in realistic circuit operations including AC mode which was further validated with modeling [1]. SRAM and product reliability results including SER also exceeds goal.

An Efficient Multiple Cell Upsets Tolerant Content-Addressable Memory

Multiple cell upsets (MCUs) become more and more problematic as the size of technology reaches or goes below 65 nm. The percentage of MCUs is reported significantly larger than that of single cell upsets (SCUs) in 20 nm technology. In SRAM and DRAM, MCUs are tackled by incorporating single-error correcting double-error detecting (SEC-DED) code and interleaved data columns. However, in content-addressable memory (CAM), column interleaving is not practically possible. A novel error correction code (ECC) scheme is proposed in this paper that will cater for ever-increasing MCUs. This work demonstrated that m parity bits are sufficient to cater for up to m-bit MCUs, with an understanding of the physical grouping of MCUs. The results showed that the proposed scheme requires 85% fewer parity bits compared to traditional Hamming distance based schemes.

Experimental study on BTI variation impacts in SRAM based on high-k/metal gate FinFET: From transistor level Vth mismatch, cell level SNM to product level Vmin

Aging induced variability has been shaving away the design margins in advanced SRAM which may become more serious with highly scaled process node. This paper provides a systematical study of the BTI variation impacts in FinFET SRAM based on 14nm 128Mbit SRAM, including the characterization from transistor and cell level to product. For transistor level, despite the effective process optimization for BTI shifts, SRAM transistor Vth mismatch shows non-negligible increase after aging due to the intrinsic Sqrt(1/WL) BTI variability trend as time=0 variations. For cell level, BTI distribution is found to be the dominant factor comparing with the circuit level parameters such as Vdd or inverter (PU/PD) ratio in terms of read SNM shifts after aging. An empirical model of EOL SNM is further proposed for the circuit level quick evaluation and HTOL fail prevention. For product level, the FBC (Failure Bit Count) slope from cell-to-cell variation and Vmin distribution from chip-to-chip variation also show non-negligible impacts due to BTI variability. The results indicate that besides the process optimization for BTI mean shifts, reliability aware circuit design is necessity to consider intrinsic BTI variation increase with transistor scaling down.

Memory reliability model for accumulated and clustered soft errors

The soft error rate of memories is increased by high-energy particles as technology shrinks. Single-error correction codes (SEC), scrubbing techniques and interleaving schemes are the most common approaches for protecting memories from soft errors. It is essential to employ analytical models to guide the selection of interleaving distance; relying on rough estimates may lead to unreasonable design choices. The analytic model proposed in this paper includes row clustering effects of accumulated upsets and was able to estimate the failure probability with only a difference of 0.41% compared to the test data for a 45nm SRAM design.

Investigation of logic circuit soft error rate (SER) in 14nm FinFET technology

This paper presents characterization results of soft error rate (SER) on logic circuits manufactured with 14 nm High-k/metal gate bulk FinFET technology. The FinFET SER advantage seen on SRAM was also validated on logic circuits (5-10X improvement). Alpha irradiation results reveal that charge collection only on NMOS on low critical charge can contribute to SEU. Adding NMOS on low critical charge can increase error rate, yet it can be easily mitigated by the design change. Design schemes for low-power has little impact to the SER. Single event transient on clock-line in 14 nm FinFET was substantially improved from planer-MOS.