Sanjay Mitra

Process variations in use for the first generations of FRAM® memory products

Abstract Ferroelectric memories have been firmly established commercially over the past decade. This paper presents the process variations used by Ramtron for its portion of the worldwide FRAM output and discusses the reasons why the particular process was chosen for each case. The first ferroelectric memory produced in volumes exceeding millions of units was the FM1208 4Kb parallel part in 1992. The exact process for the fabrication of this part at the wafer level involves a combined salicide and silicide process for the successful integration of ferroelectric materials. Furthermore, a special packaging technique is employed to minimize the effect of hydrogen and stress in the plastic packaging mold compound. Current generations of FRAM no longer have the requirement for special processing or materials at assembly. Current generation IC card products are clearly state-of-the art as programmed contents of the chip are easily retained through the card packaging process. Test and quality methods and results are reviewed.

Retention performance of sbtn semiconductor memory products

Abstract This study seeks to determine the feasibility and suitability of SBTN as a ferroelectric material used in the semiconductor wafer fabrication process. While Ramtron has years of experience producing PZT based parts, one vision for the future is that different materials may be required for different applications, depending on the specific product requirements. The family of bismuth layered perovskites may provide a path to low voltage applications, if the problems related to process integration and manufacturing that cause low bit count failures can be controlled. The design, manufacturing process and assembly are described, then a detailed evaluation is undertaken regarding retention performance.

A demonstration of low voltage performance, from scaled PLZT films, on a fully integrated 64K FRAM®

Abstract One of the prevailing concerns regarding the PLZT based system has been in its scalability for low voltage operation. Through process enhancements, a sputtered PLZT film with Calcium and Strontium dopants, has been optimized on a platinum electrode system and scaled for low voltage operation. This paper will present general background data covering the optimization of the Ferroelectric film and SOIC “Plastic” package results for a fully integrated 64k FRAM® incorporating this film.

A method of characterizing sense amplifier imbalance issues on a 2T2C FRAM® memory

Abstract FRAM® Memory Products manufactured by Ramtron International Corp., which are currently in mass production use the 2T2C cell architecture. For the correct and reliable operation of this 2T2C FRAM® memory, it is very critical that the sense amplifiers are well balanced. Any imbalance in the sense amplifiers would cause a data state preference and lead to data retention or functional failures that would compromise the yield and reliability of the product. It is very possible that inherent sense amplifier imbalances will not show up till the switching in the ferroelectric capacitors has been sufficiently degraded due to extended bakes or other stress conditions. This could lead to a scenario where these inherent sense amplifier imbalance issues are not comprehended till the product is well into its production build and qualification process. In a mass production and timeline driven project this is not an acceptable situation. This paper will discuss a simple and patented testing technique at wafer le...

An optimized package test methodology for testing FRAM® memories

Abstract As the market for ferroelectric semiconductor memories matures, the FRAM® products manufactured by Ramtron International Corp are moving into mass production. In this scenario, the optimization of the production test flow becomes a key consideration in the profitability of the product. Ramtron International Corp has thus been focussing on developing an optimized production test flow without compromising the final quality of the product.

Optimization of plastic packaging of ferroelectric semiconductor memories

Abstract As the market for ferroelectric semiconductor memories matures, optimizing the assembly flow of these memories into plastic devices becomes a key consideration in the profitability of a product. In this paper, we will propose an optimized assembly flow that will improve retention yields and product reliability. This new flow reduces the time at elevated temperature which has been known to cause compensation shift of the hysteresis loop and a reduction of ferroelectric switching. Typically, combined cures during plastic assembly of ferroelectric memories can be as long as 10 hours at temperatures which activate the imprint mechanism as they approach the Curie point. Current processes use ink cures, wafer mount cures, die attach cures, wire bonding, die coat cures, molding, molding cures and, back and top marking cures. We will review a completed analysis that introduces a thermal budget, or a reduction of time at temperature, for four of these process steps; die attach cures, die coat cures, moldi...

A qualitative model for degradation of FRAM® products during plastic packaging

Abstract A model for plastic package degradation of FRAM products involving both the thermal budget of the assembly process and the hydrogen evolution from the mold compound is proposed. Qualitative verification of the model is presented by utilizing ferroelectric aging data and failed bit analysis of the defective parts along with the measured hydrogen evolution from the three mold compounds. The implications of the model on the choice of plastic mold compound are discussed.