Tom Davenport

Addition of Ca and Sr in PLZT to improve fram® performance and reliability

Abstract Although endurance frequently receives the most attention when considering the use of ferroelectrics in memory devices, we find that retention is actually the more important concern. In particular, ferroelectric materials are prone to imprinting which is a tendency to form a preferred state. Once a preferred state is formed, memory failure can occur when trying to set the ferroelectric in the non-preferred state. In order to improve the resistance to imprint, calcium and strontium dopants in PLZT have been studied. The calcium and strontium were varied using multiple sputtering targets along with ICP to determine the composition. These films were then characterized for orientation, switching and imprint.

High endurance scaled plzt thin films for fram applications

Abstract Lower operating voltage is one of the main requirements of future generation FRAM. In order to achieve this requirement, PLZT thin film capacitors must be scaled down with respect to thickness. This paper presents the ferroelectric performance of scaled PLZT thin films. The thickness of RF magnetron sputtered PLZT thin films was scaled down to 1000Å. Integrated array capacitors (measured after local interconnect formation) using the scaled 1000Å PLZT thin films showed good switching performance, excellent endurance (fatigue free up to 1012 fatigue cycles) and good data retention. An approach to accelerate the fatigue process using high electric field is introduced in order to shorten the endurance testing time at extended fatigue cycles such as above 1011 cycles. The thickness scaled PLZT thin films, showing dramatically improved ferroelectric performance, can be applied to the manufacturing of low voltage FRAM products.

Process variations in use for the first generations of FRAM® memory products

Abstract Ferroelectric memories have been firmly established commercially over the past decade. This paper presents the process variations used by Ramtron for its portion of the worldwide FRAM output and discusses the reasons why the particular process was chosen for each case. The first ferroelectric memory produced in volumes exceeding millions of units was the FM1208 4Kb parallel part in 1992. The exact process for the fabrication of this part at the wafer level involves a combined salicide and silicide process for the successful integration of ferroelectric materials. Furthermore, a special packaging technique is employed to minimize the effect of hydrogen and stress in the plastic packaging mold compound. Current generations of FRAM no longer have the requirement for special processing or materials at assembly. Current generation IC card products are clearly state-of-the art as programmed contents of the chip are easily retained through the card packaging process. Test and quality methods and results are reviewed.

Process stability of ferroelectric PLZT thin film sputtering for FRAM® production

Abstract (PbLa)(Zr,Ti)O3 (PLZT) thin films were fabricated by RF magnetron sputtering. Aiming at process development for FRAM® production, PLZT films were deposited on 6-inch substrates using a 12-inch ceramic target. High deposition rate was realized at relatively low sputtering power by utilizing a high-density PLZT target. Precise compositional control was achieved by controlling sputtering condition. A non-stop 1000-wafer deposition was performed showing high process stability in terms of both deposition rate and ferroelectric properties.

Retention performance of sbtn semiconductor memory products

Abstract This study seeks to determine the feasibility and suitability of SBTN as a ferroelectric material used in the semiconductor wafer fabrication process. While Ramtron has years of experience producing PZT based parts, one vision for the future is that different materials may be required for different applications, depending on the specific product requirements. The family of bismuth layered perovskites may provide a path to low voltage applications, if the problems related to process integration and manufacturing that cause low bit count failures can be controlled. The design, manufacturing process and assembly are described, then a detailed evaluation is undertaken regarding retention performance.