Sanjay Sengupta

CONCAT: CONflict Driven Learning in ATPG for Industrial designs

In this paper, we propose a new search technique for ATPG, called CONCAT [1], which (a) is based on AND/OR reasoning, (b) integrates conflict driven learning, and (c) avoids over specification of test vectors. The technique works seamlessly (i) between Boolean and non-Boolean gates in industrial designs, (ii) across phases in latch-based designs, (iii) between justification and propagation tasks in sequential ATPG, and (iv) across faults in the fault list. Experimental results on combinational ISCAS circuits against SAT-based ATPG, show that we can reduce the test vector specification by upto 74%, with consistent improvement in performance and capacity. We integrated the CONCAT technique into Intels existing ATPG tool, called Aztec, and obtained upto 67% speed-up and upto 14% more ATPG effectiveness on industrial designs.

Impact and cost of modeling memories for ATPG for partial scan designs

Automatic Test Pattern Generation (ATPG) for state-of-the-art commercial grade circuits is far more complex and requires much more engineering than for the ISCAS benchmark circuits. One among the several reasons for this increased complexity is the presence of embedded memories or register arrays in the circuit. Most ATPG research has focussed solely on algorithmic techniques for test generation disregarding much of the engineering aspects required to make automatic test generation a commercial reality. While commercial ATPG tools have provides memory simple primitives to model memories, a significant amount of expertise, research and design rule checking is required to utilize the ATPG provided primitives to usefully model memories and obtain substantial amounts of additional fault-coverage in a true partial scan industrial design of considerable size. In this paper we discuss a memory modeling methodology that shows promise and we present results to show its effectiveness in terms of increased fault-coverage.

Low Coverage Analysis using dynamic un-testability debug in ATPG

In this paper, we propose an automated technique to identify the reasons for un-testable faults and, an interactive Low Coverage Analysis flow to expedite the coverage analysis step, in scan ATPG. We seamlessly use an implication graph to keep track of the reasons that are responsible for each conflict encountered during ATPG. As ATPG progresses, for each fault, all the reasons arising from ATPG constraints are logged systematically. Then, we use a low coverage analysis flow to cumulatively analyze the faults and reasons / ATPG constraints. We integrated the proposed technique into the production scan ATPG flow at Intel. The proposed technique resolved up to 15% coverage gap on real micro-processor designs in a few hours. Potentially, this would have, otherwise, taken a few days of manual effort with considerable design knowledge.

Test strategies for nanometer technologies

The trend toward bigger systems-on-a-chip means that the increase in die size alone add significant DPM, making the goal of double-digit DPM using current methods infeasible. To keep quality under control in nanometer processes, test must target delay defects, noise and process variation. Functional testing of high-performance parts continues to screen significant unique DPM on top of high coverage scan content. The at-speed tests result in heavy yield losses because they are applied in non-native mode, and could target functionally unsensitizable paths. In addition DFT supports reliable at-speed test application methods. With the proliferation of subtle defect types in nanometer processes, targeting defects directly is essential to contain test data volume. To target the defects stochastic process such as N-defect and BIST were used.

A Cube-Aware Compaction Method for Scan ATPG

We propose a test-cube aware dynamic compaction method for reducing the test set size generated by scan ATPG. In the initial phase of ATPG, when the generated test cubes are significantly compatible, we start with a local cube merging approach. Then, we switch to a compacted cube-generation approach, when the compatibility of test cubes decrease. We propose efficient heuristics for merging test cubes and writing them out during the cube-merging phase. We introduce a novel reasoning analysis technique to learn cube-independent untestable faults and, avoid targeting them repeatedly during the compacted-cube generation phase. On latest Intel microprocessor designs, we are able to achieve up to 2.3X compaction with 20% run-time over-head, on top of on-chip hardware compression.

A scan pattern debugger for partial scan industrial designs

In this paper, we propose an implication graph based sequential logic simulator for debugging scan pattern failures encountered during First Silicon. A novel Debug Implication Graph (DIG) is constructed during logic simulation of the failing scan pattern. An efficient node traversal mechanism across time frames, in the DIG, is used to perform the root-cause analysis for the failing scan-cells. We have developed an Interactive Pattern Debug environment (IDE), viz. scan pattern debugger, around the logic simulator to systematically analyze and root-cause the failures. We integrated the proposed technique into the scan ATPG flow for industrial microprocessor designs. We were able to resolve the First Silicon logical pattern failures within hours, which would have otherwise taken a few days of manual effort.