Sanjeev Rai

Analytical surface potential modeling and simulation of junction-less double gate (JLDG) MOSFET for ultra low-power analog/RF circuits

In this paper, a simple structure for short channel junction-less double gate (JLDG) MOSFET is proposed. Further expression for surface potential of JLDG has been derived using 2D Poissons equation. Based on the proposed analytical model for surface potential distribution along channel thickness and channel length is derived. The proposed junction-less MOSFET has no p-n junction as the doping of channel is same to that of Source/Drain region. The analytical model is compared with numerical solution using ATLAS device simulator. The result shows the variation of channel potential with channel length, channel thickness, doping concentration and applied gate bias. Further, in this paper the analog performance and RF figure of merits (FOMs) have been investigated. The purpose of this research is to provide a physical explanation for improved analog and RF performance exhibited by the device. In this paper major FOMs such as trans-conductance (gm), output conductance (gd), early voltage (VEA), intrinsic gain (AV), trans-conductance generation factor (TGF), cut-off frequency (fT), trans-conductance frequency product (TFP), gain frequency product (GFP), gain trans-conductance frequency product (GTFP) are analyzed. The simulation result shows that the JLDG exhibit a higher trans-conductance, higher cut-off frequency and lower drain conductance.

Modelling, Design, and Performance Comparison of Triple Gate Cylindrical and Partially Cylindrical FinFETs for Low-Power Applications

The FinFETs recently have been the rallying point for the engineers as far as the development of the technology is concerned. The authors here have tried successfully to compare the performance of 30 nm conventional triple gate (Conv) FinFET structure with that of partially cylindrical (PC) FinFET. In PC-FinFET the fin is divided into two regions. Region I is partially cylindrical and has curvature of half of the fin width, and Region II is like a conventional FinFET (having flat region). The results show that there is considerable improvement in Ion, Ioff, and subsequent suppression of short channel effects, that is, subthreshold slope, DIBL, self heating effect, and so forth. The improvement has also been felt in series resistance in PC-FinFET as compared to C-FinFET. It is noteworthy also to mention that in PC-FinFET the corner of fin is rounded thus reducing the side wall area which further reduces the gate capacitance reducing the intrinsic delay. The DC and transient analysis of CMOS inverter using C-FinFET and PC-FinFET have been done which shows that PC-FinFET inverter has reduced propagation delay as compared to C-FinFET.

A robust design for ultra low power operation using dynamic threshold SCL logic

This paper presents a novel approach to design robust source coupled logic for implementing ultra low power circuits. In this paper, we proposed a dynamic threshold source coupled logic and analyses the performance of dynamic threshold source coupled logic with previous source coupled logic for ultra low power operation. Dynamic threshold source coupled logic circuits exhibit a better power-delay Performance compared with the Sub-threshold Source Coupled Logic. It can be seen that the proposed circuit provides 56% reduction in power delay product. The proposed circuit provides lower sensitivity to temperature and power supply variation, with a superior control on power dissipation [1]. Measurements of test structures are simulated in 0.18 μm CMOS technology show that the proposed dynamic threshold source coupled l logic concept can be utilized successfully for bias currents as low as 1 pA[2]. Measurements show that existing standard cell libraries offer a good solution for ultra low power SCL circuits.

High-speed and low power unified dual-field multiplier in GF (P) and GF (2 m )

This paper presents a new hardware architecture for a unified multiplier, which operates in two types of finite field: GF (P) and GF (2m). We present a simple but highly useful modification of the conventional hardware implementation of accumulation in finite field over GF (P) and GF (2m). This new design uses parallel ones counters to accumulate the binary partial product bit in GF (P) and further uses a T flip-flop for binary extension field. The proposed multiplier in GF (2m) achieves 11.76% and 30.23% gain in speed for (8, 16, 32) and (64, 128) bit operands respectively and an average 3.92% reduction in power consumption. The unified dual field multiplier achieves 19.3% and 14.3% gain in speed and reduction in power consumption respectively for 8 bits operand. The proposed multiplier is scalable for operands of any size. The multiplier uses the LSB-first bit serial architecture for multiplication in GF (P) and GF (2m), other than Montgomery multiplication algorithm, which mostly employs existing dual field multipliers.

A study and comparative analysis of low power hybrid-CMOS 1-bit full adders in deep-submicron technology

In this paper, a review study and analysis of 1-bit full adder designs is presented with different logic styles such as Hybrid pass logic with static CMOS (HPSC), Hybrid and Hybrid-CMOS. Different styles of logic structures are used to design hybrid-CMOS namely pass transistor logic, complementary pass transistor logic (CPL), swing restoration CPL (SR-CPL) etc. So far the hybrid logic style provides a higher degree of freedom for researcher and designer to target manifold applications. All the full adder circuits have been designed in CADENCE Virtuoso environment at 45nm technology and comparison is done based on various performance parameters such as power dissipation, delay, noise margin and Power-delay product (PDP).

Reliability analysis of Junction-less Double Gate (JLDG) MOSFET for analog/RF circuits for high linearity applications

Junctionless double gate (JLDG) MOSFET in sub nano meter regime has been the preferred choice for researchers as the leakage current in a JLDG MOSFET is significantly less compared to junction based double gate (DG) MOSFET. Also since the conduction mechanism in JLDG MOSFET is bulk conduction instead of surface channel conduction, the short channel effects (SCEs) get significantly reduced. In this research paper, major reliability issues concerning JLDG MOSFET has been studied and discussed. This research paper considers the gate misalignment effect and analysis of the thermal stability by subjecting the temperature variation from 200K to 500K. Gate misalignments is one of the major reliability issues and with enhancement in second order effects, it causes reduction in on current that degrades the performance of a JLDG MOSFET. The alignment between front and back gate critically influences the performance of a JLDG device. Misalignment effect in the device occurs due to shift in the back gate either towards the drain side or the source side. The gate misalignment therefore introduces some non-ideal effects from overlap or non-overlap regions. Thermal stability of the device has been tested for operating the device over a wide range of temperatures ranging from 200K to 500K, so that the effect of temperature on the performance issues remains limited. Further, the analog/RF performance parameters have been evaluated and linearity distortion analysis due to gate misalignment effect in terms of major performance matrices has been investigated. The investigated results show that there exist a thermally stable point in and around which if the device operates would be more stable. This paper considers the gate misalignment effect that degrades the performance of device.Gate misalignment causes reduction in on current with enhancement in second order effects.Analysis of the thermal stability by subjecting the temperature variation from 200 K to 500 K.Thermal stability has been tested so that the effect of temperature on the performance issues remains limited.The analog/RF performance and linearity distortion analysis due to gate misalignment effect has been investigated.Result shows that there exist a thermally stable point in and around which if the device operates would be more stable.

Modeling, Simulation, and Analysis of Novel Threshold Voltage Definition for Nano-MOSFET

Threshold voltage (VTH) is the indispensable vital parameter in MOSFET designing, modeling, and operation. Diverse expounds and extraction methods exist to model the on-off transition characteristics of the device. The governing gauge for efficient threshold voltage definition and extraction method can be itemized as clarity, simplicity, precision, and stability throughout the operating conditions and technology node. The outcomes of extraction methods diverge from the exact values due to various short-channel effects (SCEs) and nonidealities present in the device. A new approach to define and extract the real value of VTH of MOSFET is proposed in the manuscript. The subsequent novel enhanced SCE-independent VTH extraction method named “hybrid extrapolation VTH extraction method” (HEEM) is elaborated, modeled, and compared with few prevalent MOSFET threshold voltage extraction methods for validation of the results. All the results are verified by extensive 2D TCAD simulation and confirmed analytically at various technology nodes.

Ultra-Thin High-K Dielectric Profile Based NBTI Compact Model for Nanoscale Bulk MOSFET

Negative Bias Temperature Instability (NBTI) is a key reliability and consistency issue for ultra-scaled Silicon IC technology with substantial consequences on both analog and digital circuit design For nano devices, NBTI apparently increases the threshold voltage exponentially on transient platform consequently, decreases the drain current and transconductance in the similar manner. The threshold voltage recovery function manifests the logarithmic transient reliance. The issue is of critical perturb, especially in p-channel nanoscale MOS devices, as these devices generally operate with negative gate-to-source voltage Use of high-K dielectric stack enhances the NBTI impact on these nano devices The manuscript investigates and models the NBTI characteristics for bulk driven nanoscale p-MOS device with ultrathin high-K gate dielectric stack. The gate terminal is transiently negatively biased and further relaxed with positive bias conditions for ample time for the recovery of the initial characteristics. Threshold voltage shift at various gate bias conditions and diverse temperatures demonstrate that NBTI is highly subjugated by the defect generation and hole trapping bustle in gate dielectric pre-existing traps NBTI recovery is accelerated by increasing the temperature. Threshold voltage shift in recovery phase showed a swift initial transient, ensued by an acutely sluggish, passive non-exponential transient. A compact NBTI model for nano MOSFET is proffered capturing the dependency of stress phase gate bias, recovery gate voltage and operating temperature Importantly, only the restricted bunch of fitting parameters are required for anticipation. The proposed NBTI model is valid for FD/SOI/FinFET technology also and can be easily implemented on TCAD circuit simulators.

Analytical model and performance investigation of electric potential for junctionless cylindrical surrounding gate (JLCSG) MOSFET

In this paper expression for surface potential of a junction less cylindrical surrounding gate (JLCSG) MOSFET has been derived using 2D Poissons equation. The proposed JLCSG MOSFET has no source/drain junction as the doping of channel region is the same as that of source/drain region. The analytical results are compared with the numerical solution using 2D device simulator. The result shows the variation of channel potential with the applied gate and drain bias voltage. The electrostatic parameters of JLCSG MOSFET such as subthreshold swing (SS), ION/IOFF ratio, the threshold voltage (Vt) and drain induced barrier lowering (DIBL) are investigated through exhaustive device simulation. Further, in this paper various analog/RF performance parameters have also been investigated. The performance figure of merits (FOMs) shows that the proposed device has bright future in higher speed and low power communication circuit applications.

Comparative analysis of junctionless bulk and SOI/SON FinFET

The characteristics of junctionless(JL) SON(Silicon on Nothing) FinFET, JL Bulk FinFET and SOI(Silicon on Insulator) JNT(Junctionless nanowire transistor) transistors were compared. A Silicon on nothing transistor have substrate with air filled dielectric. JL SON FinFET have better on/off current ratio and short channel effect (SCE) by reducing channel thickness due to substrate channel junction. The subthreshold slope is 63.2m V/dec and DIBL 82.68mV. the on/off current ratio is approximately 105 at channel thickness of 10nm. The variation in threshold voltage as Nsub varies from 1017 to 1018 cm−3 is about 33%. JL SON FinFET gives better on/off current ratio with the variation of work function.