R. A. Mishra

Design of High-performance Digital Logic Circuits based on FinFET Technology

gate FinFET is a novel device structure used in the nanometer regime, whereas the conventional CMOS technologys performance deteriorates due to increased short channel effects (SCEs). Double-gate (DG) FinFETs has better SCEs performance compared to the conventional CMOS and stimulates technology scaling. In this paper, we are designing 32nm DGFinFETs and extracting their characteristics by using Sentaurus TCAD, Simulated results of the device show that it can be governed at the nanometer - scale regime. DGFinFET has independent gates; threshold voltage of one gate can be altered by varying the voltage at the other gate. By using this phenomenon logic circuit can be configured in one of the modes such as SG mode, LP mode, IG mode and IG/LP mode. INVERTER and NAND gate are designed in the above mentioned node and comparison has been drawn between them. Based on the simulated results SG-mode is adequate for high- performance design.

DFAL: Diode-Free Adiabatic Logic Circuits

The manufacturing advances in semiconductor processing (continually reducing minimum feature size of transistors, increased complexity and ever increasing number of devices on a given IC) change the design challenges for circuit designers in CMOS technology. The important challenges are low power high speed computational devices. In this paper a novel low power adiabatic circuit topology is proposed. By removing the diode from the charging and discharging path, higher output amplitude is achieved and also the power dissipation of the diodes is eliminated. A mathematical expression has been developed to explain the energy dissipation in the proposed circuit. Performance of the proposed logic is analyzed and compared with CMOS and reported adiabatic logic styles. Also the layout of proposed inverter circuit has been drawn. Subsequently proposed topology-based various logic gates, combinational and sequential circuits and multiplier circuit are designed and simulated. The simulations were performed by VIRTUOSO SPECTRE simulator of Cadence in 0.18 μm UMC technology. In proposed inverter the energy efficiency has been improved to almost 60% up to 100 MHz in comparison to conventional CMOS circuits. The present research provides low power high speed results up to 100 MHz, and proposal has proven to be used in power aware high-performance VLSI circuitry.

Leakage current minimization in dynamic circuits using sleep switch

A new circuit technique is proposed in this literature to simultaneously reduce subthreshold leakage as well as gate-oxide leakage in ultra-deep submicron technology, as gate leakage is dominant for ultra thin gate insulating layer (i.e. tox >; 20Å̊). Here we are using the dual threshold voltage technique to reduce the leakage current as well as propagation delay and sleep switches to further reduce leakage current. We observed the further leakage current reduction of about 11.21% by using proposed DTPMOS sleep switch, and by using proposed stacked PMOS sleep switch is about 37.63%. Whereas, further reduction in propagation delay by using DTPMOS sleep is about 16.87% and by using stacked PMOS is about 14.97%. We have also seen that the discharging of dynamic node is more for DTMOS configuration, which is advantageous in term of reduction in leakage current when we will use multistage cascaded configuration.

Modelling, Design, and Performance Comparison of Triple Gate Cylindrical and Partially Cylindrical FinFETs for Low-Power Applications

The FinFETs recently have been the rallying point for the engineers as far as the development of the technology is concerned. The authors here have tried successfully to compare the performance of 30 nm conventional triple gate (Conv) FinFET structure with that of partially cylindrical (PC) FinFET. In PC-FinFET the fin is divided into two regions. Region I is partially cylindrical and has curvature of half of the fin width, and Region II is like a conventional FinFET (having flat region). The results show that there is considerable improvement in Ion, Ioff, and subsequent suppression of short channel effects, that is, subthreshold slope, DIBL, self heating effect, and so forth. The improvement has also been felt in series resistance in PC-FinFET as compared to C-FinFET. It is noteworthy also to mention that in PC-FinFET the corner of fin is rounded thus reducing the side wall area which further reduces the gate capacitance reducing the intrinsic delay. The DC and transient analysis of CMOS inverter using C-FinFET and PC-FinFET have been done which shows that PC-FinFET inverter has reduced propagation delay as compared to C-FinFET.

Leakage Power Analysis of Domino XOR Gate

Two new XOR gates are proposed. First proposed circuits adopt hybrid transistor topology in the pull-down network with all transistors being low threshold voltages. A second proposed circuit adopts hybrid topology with dual threshold voltage transistors. Simulation parameters are measured at 25°C and 110°C. First proposed circuit reduces leakage power consumption up to 50% at 25°C and 58% at 110°C as compared to standard N-type domino XOR gate. It also reduces active mode power consumption by 14% as compared to standard N-type domino XOR gate. Similarly, second proposed circuit reduces leakage power consumption up to 73% at 25°C and 90% at 110°C as compared to standard N-type domino XOR gate. It also reduces active mode power consumption by 39% as compared to standard N-type domino XOR gate.

Conditional Precharge Dynamic Buffer Circuit

ABSTRACT In this paper, footless domino logic buffer circuit is proposed. It minimizes redundant switching at the dynamic and the output nodes. This circuit passes propagation of precharge pulse to the dynamic node and avoids precharge pulse to the output node which saves power consumption. Simulation is done using 0.18μm CMOS technology. We have calculated the power consumption, delay and power delay product of proposed circuit and compared the results with existing circuits for different logic function, loading condition, clock frequency, temperature and power supply. For capacitance 500fF, our proposed circuit reduces power consumption by 72.69%, 26.35% and 24.03% as compared to standard footless domino, SP-Domino and SSPD techniques.

Low-power adiabatic computing with improved quasistatic energy recovery logic

Efficiency of adiabatic logic circuits is determined by the adiabatic and non-adiabatic losses incurred by them during the charging and recovery operations. The lesser will be these losses circuit will be more energy efficient. In this paper, a new approach is presented for minimizing power consumption in quasistatic energy recovery logic (QSERL) circuit which involves optimization by removing the nonadiabatic losses completely by replacing the diodes with MOSFETs whose gates are controlled by power clocks. Proposed circuit inherits the advantages of quasistatic ERL (QSERL) family but is with improved power efficiency and driving ability. In order to demonstrate workability of the newly developed circuit, a 4 × 4 bit array multiplier circuit has been designed. Amathematical expression to calculate energy dissipation in proposed inverter is developed. Performance of the proposed logic (improved quasistatic energy recovery logic (IQSERL)) is analyzed and compared with CMOS and reported QSERL in their representative inverters and multipliers in VIRTUOSO SPECTRE simulator of Cadence in 0.18 µm UMC technology. In our proposed (IQSERL) inverter the power efficiency has been improved to almost 20% up to 50MHz and 300 fF external load capacitance in comparison to CMOS and QSERL circuits.

Performance Improvement of GFCAL Circuits

this paper authors have presented a new approach to improve the performance of the glitch free cascadable adiabatic logic (GFCAL) circuit by replacing the triangular power supply with sinusoidal and trapezoidal power supplies (that control the charging and discharging of the capacitive load) and by sizing of transistors. A simulative investigation and performance analysis of proposed approach based 3 bit GFCAL counter, GFCAL JK flip flop and GFCAL 6T-SRAM circuit have also been done. The triangular power supply produces very large delay at the outputs of GFCAL circuits thus it will be very difficult to cascade larger circuits. A solution to provide cascadability is optimization of the delay. In the proposed approach the delay of GFCAL counter for triangular supply has been improved about 40% and 60% whereas for JK flip flop it is 46% and 49% and for 6T SRAM it is 17% and 91% with sinusoidal and trapezoidal power clocks respectively. Keywordscircuit, MOS-Diode, Switching activity.

A survey on different keeper design topologies for high speed wide AND-OR domino circuits

In this paper, we analyze and compare different keeper design topologies for lowering the active mode power consumption, increasing the speed, enhancing the noise immunity and reducing the subthreshold leakage energy of domino logic circuits. This work briefly surveys domino keeper techniques for high fan-in domino circuits. We compared the power, delay, process tracking and VDD tracking of different topologies. These topologies have been prototyped in 130nm CMOS technology at 125°C temperature. The simulation results reveal that conditional keeper technique gives the better results in terms of reduction in delay, power consumption whereas Leakage current replica (LCR) based keeper shows superior performance in terms of noise overhead, process variation and VDD tracking as compared to other alternatives keepers. As compare to conventional circuit, conditional keeper gives 55% reduction in delay as well as 15% reduction in power while leakage current replica (LCR) gives 95% reduction in noise overhead and providing capability of process and VDD tracking.

Comparative analysis of junctionless bulk and SOI/SON FinFET

The characteristics of junctionless(JL) SON(Silicon on Nothing) FinFET, JL Bulk FinFET and SOI(Silicon on Insulator) JNT(Junctionless nanowire transistor) transistors were compared. A Silicon on nothing transistor have substrate with air filled dielectric. JL SON FinFET have better on/off current ratio and short channel effect (SCE) by reducing channel thickness due to substrate channel junction. The subthreshold slope is 63.2m V/dec and DIBL 82.68mV. the on/off current ratio is approximately 105 at channel thickness of 10nm. The variation in threshold voltage as Nsub varies from 1017 to 1018 cm−3 is about 33%. JL SON FinFET gives better on/off current ratio with the variation of work function.