Sanjiv Narayan

Specification and design of embedded systems

1. Introduction. 2. Models and Architectures. 3. Specification Languages. 4. A Specification Example. 5. Translation to VHDL. 6. System Partitioning. 7. Design Quality Estimation. 8. Specification Refinement into Synthesizable Models. 9. System-Design Methodology and Environment. Appendix: Answering Machine in SpecCharts. Bibliography. Index.

SpecSyn: an environment supporting the specify-explore-refine paradigm for hardware/software system design

System-level design issues are gaining increasing attention, as behavioral synthesis tools and methodologies mature. We present the SpecSyn system-level design environment, which supports the new specify-explore-refine (SER) design paradigm. This three-step approach to design includes precise specification of system functionality, rapid exploration of numerous system-level design options, and refinement of the specification into one reflecting the chosen option. A system-level design option consists of an allocation of system components, such as standard and custom processors, memories, and buses, and a partitioning of functionality among those components. After refinement, the functionality assigned to each component can then he synthesized to hardware or compiled to software. We describe the issues and approaches for each part of the SpecSyn environment. The new paradigm and environment are expected to lead to a more than ten times reduction in design time, and our experiments support this expectation.

Interfacing Incompatible Protocols Using Interface Process Generation

During system design, one or more portions of the system may be implemented with standard components that have a fixed pin structure and communication protocol. This paper described a new technique, interface process generation, for interfacing standard components that have incompatible protocols. Given an HDL description of the two protocols, we present a method to generate an interface process that allows the two protocols to communicate with each other.

A system-design methodology: executable-specification refinement

As methodologies and tools for chip-level design mature, design effort becomes focused on increasingly higher levels of abstraction. We present a methodology and tool for system-level specification, design and refinement that result in an executable specification for each system component. The specification for each component can then be synthesized into hardware or compiled to software. We highlight advantages of the proposed methodology compared to current practice.<<ETX>>

Synthesis of system-level bus interfaces

Given a set of communication channels to be implemented as a single bus, the authors present a bus-generation algorithm which determines the width of a bus implementation. Tradeoffs between the width of the bus and the performance of the processes communicating over the bus are evaluated. The algorithm incorporates system level constraints such as data transfer rates and the number of pins and allows several channels that may be transferring different sizes of data to be implemented as a single bus. The authors demonstrate through a detailed example the usefulness of the algorithm in implementing system-level interfaces between modules.<<ETX>>

System specification and synthesis with the SpecCharts language

There is a need for capturing behavioral specifications of entire systems and obtaining multi-chip designs from those specifications. The authors discuss system level specification and synthesis issues, along with the unique requirements they place on a specification language. Since no current language meets those requirements, the SpecCharts language was created on top of VHDL (VHSIC Hardware Description Language). The SpecCharts language permits concise, understandable, and accurate specification of systems while supporting the concept of behavioral hierarchy, which considerably aided the specification of hardware systems modeled by the authors. Its constructs aid system level synthesis tasks such as partitioning, estimation, interface synthesis, and bus merging by permitting high level communication, and maintaining information and permitting modification at the level at which most modelers think at.<<ETX>>

System specification with the SpecCharts language

The SpecCharts language, which builds on VHDL to meet the unique requirements of system-level specification and design, is described. With an underlying model of behavioral hierarchy, SpecCharts modeling constructs enable designers to capture system specifications simply and precisely. SpecCharts constructs facilitate system-level design tasks by permitting high-level communication, maintaining information, and allowing design modification at an easy-to-comprehend level. The results of system-level design tasks are reflected in a modified SpecCharts, enabling the designer to evaluate the quality of each step. A detailed example demonstrates the use of SpecCharts.<<ETX>>

SpecCharts : A Language for System Level Synthesis

Abstract To convert a system specification to a hardware implementation, several synthesis tasks may be required prior to performing traditional high-level synthesis tasks. We discuss these system level synthesis tasks, along with the unique requirements they place on a specification language. Since no current language meets these requirements, the SpecCharts language was created. It is essentially a combination of hierarchical/concurrent state diagrams and HDL constructs. A new, general communication mechanism is introduced, which encompasses most previous attempts. Other constructs are discussed, which attempt to ease the conversion from system conceptualization to system specification, and also aid synthesis.

System clock estimation based on clock slack minimization

When estimating a hardware implementation from behavioral descriptions, an important decision is the selection of a clock cycle to schedule the datapath operations into control steps. Traditional high-level synthesis systems require the designer to specify the clock cycle explicitly or express operator delays in terms of multiples of a clock cycle. The authors present an algorithm for clock estimation from dataflow graphs, based on clock slack minimization. This will provide both designers and synthesis tools with a realistic estimate of the clock cycle that can be used to implement a design. By using real life components and examples, it is shown that the clock estimates produced by this method yield faster execution times for the designs, as compared to the maximum operator delay methods. It is observed that the designs scheduled with the clock cycle estimates have faster execution times regardless of the components finally allocated for implementing the design during synthesis.<<ETX>>

SpecCharts: a VHDL front-end for embedded systems

VHDL and other hardware description languages are commonly used as specification languages during system design. However, the underlying model of those languages does not directly support the specification of embedded systems, making the task of specifying such systems tedious and error-prone. We introduce a new conceptual model, called Program-State Machines (PSM), that caters to embedded systems. We describe SpecCharts, a VHDL extension that supports capture of the PSM model. The extensions we describe can also be applied to other languages. SpecCharts can be easily incorporated into a VHDL design environment using automatic translation to VHDL. We highlight several experiments that demonstrate the advantages of significantly reduced specification time, fewer errors, and improved specification readability. >