Santanu Kundu

Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router

Network-on-Chip (NoC) has emerged as a new paradigm to integrate large number of cores on a single silicon die. This paper presents a detailed study of Mesh-of-Tree (MoT) topology and explores its promise in communication infrastructure design for 2-D NoC. The performance and cost of MoT based NoC have been evaluated and compared with butterfly fat-tree (BFT) and two variants of mesh network for equal number of cores under same bisection width constraint. Simulation results under self-similar traffic show that MoT enjoys the advantage of having better performance than other topologies, whereas, it consumes lesser average packet energy than the mesh network that connects single core to each router. In the area front, MoT occupies almost similar area like mesh network connects single core to each router. The MoT network has also been evaluated under a set of real benchmark applications and compared with the above mentioned topologies. Simulation results under application specific traffic also show the competitive potential of MoT topology in NoC design. Moreover, due to lesser connectivity of the routers, synthesis result shows that MoT network can be operated at higher frequency than others. Taking all these facts into consideration, this paper establishes that like mesh and BFT, MoT can also be applied in designing NoC based systems. This paper also focuses on the limitations of MoT and other tree based topologies in NoC design in current technology and enumerates probable solutions to make them more acceptable.

Network-on-chip architecture design based on mesh-of-tree deterministic routing topology

Network-on-Chip (NoC) is a new paradigm for designing future System-on-Chips (SoCs) where large numbers of Intellectual Property (IP) cores are connected through an interconnection network. The communication between the nodes is achieved by routing packets rather than wires. It supports high degree of reusability, scalability, and parallelism in communication. Here, we present NoC architecture based on Mesh-of-Tree (MoT) deterministic routing. MoT interconnection has the advantage of having small diameter as well as large bisection width. It is known as the fastest network when considered solely in terms of speed. The routing algorithm ensures that the packet will always reach the destination through the shortest path and it is deadlock free. We also present how Globally Asynchronous Locally Synchronous (GALS) style of communication has been implemented by using FIFO in mixed clock system.

Mesh-of-tree deterministic routing for network-on-chip architecture

Network-on-Chip (NoC) is a new paradigm for designing future SoCs. It supports high degree of reusability, scalability, and parallelism in communication. Here, we present Mesh-of-Tree (MoT) based deterministic routing for NoC architecture. MoT interconnection has the advantage of having small diameter as well as large bisection width. The routing algorithm ensures that the packet will always reach the destination through the shortest path and it is deadlock and livelock free.

A Comparative Performance Evaluation of Network-on-Chip Architectures under Self-Similar Traffic

The actual traffic data collected on various applications specific on-chip networks exposed that the network traffic is self-similar in nature. In this work, modeling of self-similar traffic by aggregation of a large number of on-off Pareto sources has been discussed. We have developed a cycle accurate network simulator for evaluating the performance of wormhole router based network by varying locality factor and offered load. The performance of a Mesh-of-Tree (MoT) based network has been compared with mesh and Butterfly Fat Tree (BFT) based networks all having 32 cores. We have shown that MoT based networks perform better than mesh and BFT under self-similar traffic.

Interfacing Cores and Routers in Network-on-Chip Using GALS

Network-on-Chip (NoC) architectures consist of heterogeneous cores connected through an interconnection network. The communication between the nodes is achieved by routing packets rather than wires. It supports high degree of reusability, scalability, and parallelism in communication. NoC has emerged as a new paradigm for designing core based System-on-Chip (SoC). The success of NoC design relies greatly on the standardization of the interfaces between IP cores and network fabric. The cores may have different frequency, whereas the network router also may operate at different frequency as per design. So, there is a possibility of loosing some data due to improper synchronization. In this paper, we propose the design of Network Interface to make the IP core compatible to network switch, enabling communication between them. We also present how Globally Asynchronous Locally Synchronous (GALS) style of communication has been implemented in our NOC by using FIFO in mixed clock system.

Network-on-Chip : The Next Generation of System-on-Chip Integration

Introduction System-on-Chip Integration and Its Challenges SoC to Network-on-Chip: A Paradigm Shift Research Issues in NoC Development Existing NoC Examples Summary References Interconnection Networks in Network-on-Chip Introduction Network Topologies Switching Techniques Routing Strategies Flow Control Protocol Quality-of-Service Support NI Module Summary References Architecture Design of Network-on-Chip Introduction Switching Techniques and Packet Format Asynchronous FIFO Design GALS Style of Communication Wormhole Router Architecture Design VC Router Architecture Design Adaptive Router Architecture Design Summary References Evaluation of Network-on-Chip Architectures Evaluation Methodologies of NoC Traffic Modeling Selection of Channel Width and Flit Size Simulation Results and Analysis of MoT Network with WH Router Impact of FIFO Size and Placement in Energy and Performance of a Network Performance and Cost Comparison of MoT with Other NoC Structures Having WH Router under Self-Similar Traffic Simulation Results and Analysis of MoT Network with Virtual Channel Router Performance and Cost Comparison of MoT with Other NoC Structures Having VC Router Limitations of Tree-Based Topologies Summary References Application Mapping on Network-on-Chip Introduction Mapping Problem ILP Formulation Constructive Heuristics for Application Mapping Constructive Heuristics with Iterative Improvement Mapping Using Discrete PSO Summary References Low-Power Techniques for Network-on-Chip Introduction Standard Low-Power Methods for NoC Routers Standard Low-Power Methods for NoC Links System-Level Power Reduction Summary References Signal Integrity and Reliability of Network-on-Chip Introduction Sources of Faults in NoC Fabric Permanent Fault Controlling Techniques Transient Fault Controlling Techniques Unified Coding Framework Energy and Reliability Trade-Off in Coding Technique Summary References Testing of Network-on- Chip Architectures Introduction Testing Communication Fabric Testing Cores Summary References Application-Specific Network-on-Chip Synthesis Introduction ASNoC Synthesis Problem Literature Survey System-Level Floorplanning Custom Interconnection Topology and Route Generation ASNoC Synthesis with Flexible Router Placement Summary References Reconfigurable Network-on-Chip Design Introduction Literature Review Local Reconfiguration Approach Topology Reconfiguration Link Reconfiguration Summary References Three-Dimensional Integration of Network-on-Chip Introduction 3-D Integration: Pros and Cons Design and Evaluation of 3-D NoC Architecture Summary References Conclusions and Future Trends Conclusions Future Trends Comparison between Alternatives References Index

Mesh-of-Tree Based Scalable Network-on-Chip Architecture

Scalability has become an important consideration in Network-on-Chip (NoC) designs. The word scalability has been widely used in the parallel processing community. For massively parallel computing, a scalable system has the property that performance will increase linearly with the system size. The scalability analysis may be used to select the best architecture for a problem under different constraints on the growth of the problem size and the number of processors. In this paper, we have analyzed the scalability issue of Mesh-of-Tree topology based network.

FIFO Optimization for Energy-Performance Trade-off in Mesh-of-Tree Based Network-on-Chip

This paper presents an exhaustive study about the impact of FIFO optimization on performance and energy consumption in a Mesh-of-Tree (MoT) based Network-on-Chip (NoC) architecture. A generic NoC router has FIFO at each input and output channel. The paper shows that FIFO is the most energy hungry component in a NoC router. On the design trade-off front, we establish that elimination of FIFO from the output channel reduces energy consumption significantly at the cost of marginal performance degradation.

Design and Evaluation of Mesh-of-Tree Based Network-on-Chip for Two- and Three-Dimensional Integrated Circuits

This thesis presents an in-depth study of Mesh-of-Tree (MoT) topology and its application in Network-on-Chip (NoC) design for both 2-D and 3-D ICs. The performance and cost of the MoT network have been evaluated and compared with other well established topologies in NoC paradigm under self-similar traffic and a set of real benchmark applications. From simulation results, the thesis establishes MoT to be a strong contender in designing the communication infrastructure of 2-D and 3-D NoC.