Kanchan Manna

Application Mapping Onto Mesh-Based Network-on-Chip Using Discrete Particle Swarm Optimization

This paper presents a discrete particle swarm optimization (PSO)-based strategy to map applications on both 2-D and 3-D mesh-connected Networks-on-Chip. The basic PSO formulation has been augmented by: 1) running multiple PSOs and 2) deterministically generating a part of the initial population for PSO. The mapping results, in terms of the overall communication metric, have been compared with well-known techniques reported in the literature and also with exact methods built around integer linear programming (ILP). Our PSO-based results are superior to those from reported techniques. For smaller benchmarks, the results obtained are same as those corresponding to the ILP formulation, establishing the quality of the solution strategy.

A new application mapping algorithm for mesh based Network-on-Chip design

This paper presents a novel application mapping strategy onto the mesh topology for Network-on-Chip (NoC) design. Compared to the previously published works, this paper uses the approach of Kernighan-Lin bi-partitioning strategy to identify the closeness of cores by analyzing their bandwidth requirements. The nodes are then mapped to the topology using another heuristic algorithm. An iterative improvement phase refines the mapping further. Experimentation with established benchmarks shows that though the static performance of the approach is similar to the best ones previously available, there is 8–17% improvement in latency while considering dynamic communication between the cores.

Extending Kernighan–Lin partitioning heuristic for application mapping onto Network-on-Chip

Abstract This paper extends the basic Kernighan–Lin graph bi-partitioning algorithm for partitioning core graphs of applications to be designed using Network-on-Chip (NoC) concept. Mapping techniques have been developed for three different types of NoC topologies – Mesh, Mesh-of-Tree (MoT), and Butterfly-Fat-Tree (BFT). Suitable post-processing schemes have been developed to improve upon the basic solution produced by the partitioning algorithm. Significant improvement in both static and dynamic performances could be observed, compared to many existing approaches reported in the literature.

A Comparative Performance Evaluation of Network-on-Chip Architectures under Self-Similar Traffic

The actual traffic data collected on various applications specific on-chip networks exposed that the network traffic is self-similar in nature. In this work, modeling of self-similar traffic by aggregation of a large number of on-off Pareto sources has been discussed. We have developed a cycle accurate network simulator for evaluating the performance of wormhole router based network by varying locality factor and offered load. The performance of a Mesh-of-Tree (MoT) based network has been compared with mesh and Butterfly Fat Tree (BFT) based networks all having 32 cores. We have shown that MoT based networks perform better than mesh and BFT under self-similar traffic.

An Application Mapping Technique for Butterfly-Fat-Tree Network-on-Chip

This paper presents a novel application mapping strategy onto the Butterfly Fat Tree (BFT) topology for Network-on-Chip (NoC) design. It proposes a Kernighan-Lin bi-partitioning strategy to identify the closeness of cores by analyzing their bandwidth requirements. The nodes are then mapped to the BFT topology. The BFT mapping results have been compared with mesh-mapping results reported in the literature for some benchmark applications. Experimentation with established benchmarks shows that there is 30-35% improvement in communication cost while considering static communication between the cores to the best ones previously available. The dynamic performance (including latency and throughput) of this strategy is comparable with previously available mapping strategies.

A spare router based reliable Network-on-Chip design

This paper presents a fault tolerant reconfigurable Network-on-Chip (NoC) architecture using router redundancy. In case of occurrence of fault in the active router, the spare router takes its place thus the system operates normally. This scheme is topology independent, so any topology with defined routing algorithm is suitable for implementation. The system has been compared in terms of reliability, mean time to failure (MTTF) and area overhead with existing works. For a 10 × 10 mesh, it gives a 1.14 reliability gain over quad-spare mesh, 1.42 reliability gain over column-spare mesh and 21.195 reliability gain over normal mesh. The mean time to failure (MTTF) gains over column-spare, quad spare and normal mesh are 3.19, 7.51, and 33.38 respectively. We have also presented a system performance report which includes throughput and latency of the proposed design.

Mesh-of-Tree Based Scalable Network-on-Chip Architecture

Scalability has become an important consideration in Network-on-Chip (NoC) designs. The word scalability has been widely used in the parallel processing community. For massively parallel computing, a scalable system has the property that performance will increase linearly with the system size. The scalability analysis may be used to select the best architecture for a problem under different constraints on the growth of the problem size and the number of processors. In this paper, we have analyzed the scalability issue of Mesh-of-Tree topology based network.

A new application mapping strategy for Mesh-of-Tree based Network-on-Chip

This paper addresses the problem of application mapping for Mesh-of-Tree (MoT) based Network-on-Chip. It proposes a new algorithm based on Kernighan-Lin partitioning to identify closely related cores of the application. The nodes are then mapped to the topology using another heuristic algorithm. The MoT mapping results have been compared with the mesh-mapping results reported in the literature for some benchmark applications. Both static communication cost and dynamic costs (including latency and throughput) of the mapped solution have been compared.

Energy and performance evaluation of a dimension order routing algorithm for Mesh-of-Tree based Network-on-Chip architecture

This paper proposes a new dimension order routing algorithm for Mesh-of-Tree based Network-on-Chip design. It simplifies the router design as well. It results in significant saving in the energy consumed by the network. For uniform traffic, the saving is as high as 63%. It offers the flexibility of designing routers of different sizes for mapping of applications.

A Novel Technique to Reduce both Leakage and Peak Power during Scan Testing

This paper addresses the issue of blocking pattern selection to reduce both leakage and peak power consumption during circuit testing using scan-based approach. The blocking pattern is used to prevent the scan-chain transitions to circuit inputs. This though reduces dynamic power significantly, can result in quite an increase in the leakage power and peak power. We have presented a novel approach to select a blocking pattern that reduces both peak and leakage power. The avg. improvement in peak power is 31.8% and that of leakage power is 13.5% (best is around 51.2% & 24.9% respectively) with respect to all 1s vector.