Santanu Mahapatra

Realization of multiple valued logic and memory by hybrid SETMOS architecture

A novel complimentary metal-oxide-semiconductor (CMOS) single-electron transistor (SET) hybrid architecture, named SETMOS, is proposed, which offers Coulomb blockade oscillations and quasi-periodic negative differential resistance effects at much higher current level than the traditional SETs. The Coulomb blockade oscillation characteristics are exploited to realize the multiple valued (MV) literal gate and the periodic negative differential resistance behavior is utilized to implement capacitor-less multiple valued static random access memory (MV SRAM) cell. The SETMOS literal gate is then used to build up other MV logic building blocks, e.g., transmission gate, binary to MV logic encoder, and MV to binary logic decoder. Analytical SET model simulations are employed to verify the functionalities of the proposed MV logic and memory cells for quaternary logic systems. SETMOS MV architectures are found to be much faster and less temperature-sensitive than previously reported hybrid CMOS-SET based MV circuits.

Few electron devices: towards hybrid CMOS-SET integrated circuits

In this paper, CMOS evolution and their fundamental and practical limitations are briefly reviewed, and the working principles, performance, and fabrication of single-electron transistors (SETs) are addressed in detail. Some of the unique characteristics and functionality of SETs, like unrivalled integration and low power, which are complementary to the sub-20 nm CMOS, are demonstrated. Characteristics of two novel SET architectures, namely, C-SET and R-SET, aimed at logic applications are compared. Finally, it is shown that combination of CMOS and SET in hybrid ICs appears to be attractive in terms of new functionality and performance, together with better integrability for ULSI, especially because of their complementary characteristics. It is envisioned that efforts in terms of compatible fabrication processes, packaging, modeling, electrical characterization, co-design and co-simulation will be needed in the near future to achieve substantial advances in both memory and logic circuit applications based on CMOS-SET hybrid circuits.

A quasi-analytical SET model for few electron circuit simulation

A novel quasi-analytical model for single electron transistors (SETS) is proposed and validated by comparison with Monte-Carlo (MC) simulations in terms of drain current and transconductance. The new approach is based on the separate modeling of the tunneling and thermal components of the drain current, and verified over two decades of temperature. The model parameters are physical and an associated parameter extraction procedure is also reported. The model is shown to be accurate for SET logic circuit simulation in both static and dynamic regimes and is attractive for hybrid (SET-CMOS) circuit co-simulation.

Modeling of Channel Potential and Subthreshold Slope of Symmetric Double-Gate Transistor

A new physically based classical continuous potential distribution model, particularly considering the channel center, is proposed for a short-channel undoped body symmetrical double-gate transistor. It involves a novel technique for solving the 2-D nonlinear Poissons equation in a rectangular coordinate system, which makes the model valid from weak to strong inversion regimes and from the channel center to the surface. We demonstrated, using the proposed model, that the channel potential versus gate voltage characteristics for the devices having equal channel lengths but different thicknesses pass through a single common point (termed ldquocrossover pointrdquo). Based on the potential model, a new compact model for the subthreshold swing is formulated. It is shown that for the devices having very high short-channel effects (SCE), the effective subthreshold slope factor is mainly dictated by the potential close to the channel center rather than the surface. SCEs and drain-induced barrier lowering are also assessed using the proposed model and validated against a professional numerical device simulator.

Monolayer Transition Metal Dichalcogenide Channel-Based Tunnel Transistor

We investigate the gate controlled direct band-to-band tunneling (BTBT) current in monolayer transition-metal dichalcogenide (MX₂) channel-based tunnel field effect transistor (TFET). Five MX₂ materials (MoS₂,MoSe₂,MoTe₂,WS₂,WSe₂) in their 2-D sheet forms are considered for this purpose. We first study the real and imaginary band structure of those MX₂ materials by density-functional theory (DFT), which is then used to evaluate the gate-controlled current under the Wentzel-Kramers-Brillouin (WKB) approximation. It is shown that all five MX₂ support direct BTBT in their monolayer sheet forms and offer an average ON current and subthreshold slope of 150 μA/μm (at V_d=0.1 V) and 4 mV/dec, respectively. Furthermore, we also demonstrate the strain effect on the complex band structures and the performances of MX₂ based TFETs. It is observed that a certain tensile strain becomes favorable for the improvement of ON-current performances.

A Computationally Efficient Generalized Poisson Solution for Independent Double-Gate Transistors

Previous techniques used for solving the 1-D Poisson equation (PE) rigorously for long-channel asymmetric and independent double-gate (IDG) transistors result in potential models that involve multiple intercoupled implicit equations. As these equations need to be solved self-consistently, such potential models are clearly inefficient for compact modeling. This paper reports a different rigorous technique for solving the same PE by which one can obtain the potential profile of a generalized IDG transistor that involves a single implicit equation. The proposed Poisson solution is shown to be computationally more efficient for circuit simulation than the previous solutions.

Hybrid SETMOS architecture with Coulomb blockade oscillations and high current drive

A hybrid single electron transistor/MOSFET (SETMOS) circuit cell architecture, working as a three-terminal stand-alone device for obtaining SET-like Coulomb blockade oscillations, along with a high current drive ( /spl sim/ /spl mu/A), is proposed. SETMOS characteristics are successfully predicted by analytical models at subambient (-100 /spl deg/C to -150 /spl deg/C) temperature with realistic device parameters. The effect of bias voltages and current on the SETMOS Coulomb blockade oscillations characteristics is critically discussed. It is also demonstrated that the SETMOS can be converted into a unique quasi-periodic negative differential resistance (NDR) device by short-circuiting its gate and drain terminals.

Modeling and Analysis of Body Potential of Cylindrical Gate-All-Around Nanowire Transistor

A new physically based classical model for the potential distribution of an undoped body cylindrical gate-all-around nanowire transistor is proposed. The model is based on the analytical solution of 2-D Poissons equation in a cylindrical coordinate system and is valid for both (1) weak and strong inversion regimes, (2) long and short-channel transistors, and (3) body surfaces and centers. Using the proposed model, for the first time, it is demonstrated that the body potential versus gate voltage characteristics for the devices having equal channel lengths but different body radii pass through a single common point (termed a ldquocrossover pointrdquo). It is found that, at this crossover point, there is no potential drop (ldquopseudo flatband conditionrdquo) along the radial direction. Using the concept of crossover point, the effect of body radius on the threshold voltage of undoped body multigate transistors is explained. Based on the proposed body potential model, a new compact model for the subthreshold swing is formulated. It is shown that for the devices having very high short-channel effects, the effective subthreshold slope factor is mainly dictated by the potential at the body center rather than that at the surface. All the models are validated against a professional numerical device simulator.

A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated Circuits

This paper introduces a CAD framework for co-simulation ofhybrid circuits containing CMOS and SET (Single ElectronTransistor) devices. An improved analytical model for SET is alsoformulated and shown to be applicable in both digital and analogdomains. Particularly, the extension of the recent MIB model forsingle/multi gate symmetric/asymmetric device for a wide range ofdrain to source voltage and temperature is addressed. Circuit levelco-simulations are successfully performed by implementing theSET analytical model in Analog Hardware Description Language(AHDL) of a professional circuit simulator SMARTSPICE.Validation at device and circuit level is carried out by Monte-Carlosimulations. Some novel functionality hybrid CMOS-SETcircuit characteristics: (i) SET neuron (ii) Multiple valued logiccircuit and (iii) a new Negative Differential Resistance (NDR)circuit, are also predicted by the proposed SET model andanalyzed using the new hybrid simulator.

Performance Analysis of Strained Monolayer

We present a computational study on the impact of tensile/compressive uniaxial (εxx) and biaxial (εxx=εyy) strain on monolayer MoS2, n-, and p-MOSFETs. The material properties like band structure, carrier effective mass, and the multiband Hamiltonian of the channel are evaluated using the density functional theory. Using these parameters, self-consistent Poisson-Schrödinger solution under the nonequilibrium Greens function formalism is carried out to simulate the MOS device characteristics. 1.75% uniaxial tensile strain is found to provide a minor (6%) ON current improvement for the n-MOSFET, whereas same amount of biaxial tensile strain is found to considerably improve the p-MOSFET ON currents by 2-3 times. Compressive strain, however, degrades both n-MOS and p-MOS devices performance. It is also observed that the improvement in p-MOSFET can be attained only when the channel material becomes indirect gap in nature. We further study the performance degradation in the quasi-ballistic long-channel regime using a projected current method.